MIPI D-PHY Rx 2 Lanes - TSMC7FF18, North/South Poly Orientation
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
- MIPI D-PHY
- TSMC
- 7nm
- N7FF
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
MIPI D-PHY Rx 2 Lanes - TSMC7FF18, North/South Poly Orientation
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI D-PHY Tx 4 Lanes - TSMC6ff18, North/South Poly Orientation
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI D-PHY Tx 2 Lanes - TSMC6ff18, North/South Poly Orientation
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI D-PHY Rx 4 Lanes - TSMC6ff18, North/South Poly Orientation
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI D-PHY Rx 2 Lanes - TSMC6ff18, North/South Poly Orientation
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI D-PHY Rx 4 Lanes - TSMC40ULP25
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI D-PHY Rx 2 Lanes - TSMC40ULP25
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI D-PHY Bidir 4 Lanes - TSMC40ULP25
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI D-PHY BD 2 Lanes - TSMC40ULP25
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI D-PHY Tx 4 Lanes - TSMC12FFC18, North/South Poly Orientation
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI D-PHY Tx 2 Lanes - TSMC12FFC18, North/South Poly Orientation
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI D-PHY Rx 4 Lanes - TSMC12FFC18, North/South Poly Orientation
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI D-PHY Rx 2 Lanes - TSMC12FFC18, North/South Poly Orientation
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI DPHY Gen2 Rx-Only 4 Lanes - TSMC 40ULPeF 1.8V
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI DPHY Gen2 Rx-Only 2 Lanes - TSMC 40ULPeF 1.8V
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI DPHY Gen2 Bidirectional 4 Lanes - TSMC 40ULPeF 1.8V
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI DPHY Gen2 Bidirectional 2 Lanes - TSMC 40ULPeF 1.8V
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…
MIPI DPHY Gen2 Bidirectional 2 Lanes - TSMC 40LP 2.5V
The D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral d…