The Mixel Automotive SerDes Alliance Motion Link (ASA-ML) PHY is a high-speed Automotive SerDes solution compliant with the Autom…
- PHY
- ASA Motion Link
PHY and SerDes IP cores are essential building blocks for high-speed data transmission in modern semiconductor designs. This category includes physical layer IP and serializer/deserializer solutions used to implement reliable chip-to-chip, die-to-die, backplane and interface connectivity across networking, compute, storage, automotive and consumer applications.
Browse PHY / SerDes semiconductor IP for high-speed interfaces requiring robust signal integrity, scalable lane configurations, low power and standards-oriented interoperability. Compare controller-adjacent PHY IP, generic SerDes architectures and specialized high-speed connectivity solutions from multiple vendors for integration into ASICs, SoCs and advanced package designs.
The Mixel Automotive SerDes Alliance Motion Link (ASA-ML) PHY is a high-speed Automotive SerDes solution compliant with the Autom…
The 56G/64G PAM4 SERDES hard macro IP delivers a high-performance, low-power solution for high-speed serial interfaces.
Automotive Grade PLLs, Oscillators, SerDes PMAs, LVDS/CML IP
Silicon Creations supports customers in designing ICs for the automotive market by offering its comprehensive product portfolio t…
The SERDES PHY IP delivers a high-performance, low-power solution for high-speed interfaces up to 112Gbps.
SD4.x UHSII is PHY IP solution for UHS-II interface for next generation of ultra high speed used in both SDHC and SDXC.
USB Full Speed Transceiver
Size optimized, Silicon agnostic, Silicon Proven Ethernet PCS IP core for High Speed Ethernet applications The 200G/400G Ethernet…
ONFI 5.0 NAND Fash PHY IP Compliant to JEDEC
Open NAND Flash Interface (ONFI) for NAND Flash Memory chips is an open standard.
The MIPI® D-PHY RX+ is a proprietary implementation of the MIPI Camera Serial Interface 2 (CSI-2) and Display Serial Interface (D…
The MXL-DS-LVDS is a high performance 4-channel LVDS Deserializer implemented using digital CMOS technology.
The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology.
MIPI D-PHY/LVDS Combo Transmitter IP
The MXL-LVDS-DPHY-DSI-TX is a combo PHY that consists of a high-frequency low-power, low-cost, source-synchronous, Physical Layer…
Low Latency Ethernet 100G MAC and PHY Intel® FPGA IP Core
Intel® offers ultimate flexibility, scalability, and configurability with the Low Latency 100G Ethernet Intel® FPGA IP core targe…
Backplane Ethernet 10GBASE-KR PHY Intel® FPGA IP Core
The Backplane Ethernet 10GBASE-KR PHY Intel® FPGA Intellectual Property (IP) core is a transceiver PHY that allows you to instant…
Intel® Agilex™ 7 and Intel® Stratix® 10 FPGA E-Tile Hard IP
The Intel® Agilex™ 7 and Intel® Stratix® 10 FPGA E-Tile incorporates a configurable, hardened Ethernet protocol stack compatible …
40G Ethernet MAC and PHY FPGA IP Core
The 40G Ethernet MAC and PHY FPGA IP core offers IEEE 802.3ba-2010.
1G/10Gb Ethernet PHY Intel® FPGA IP
The 1G/10G Ethernet PHY Intel® FPGA Intellectual Property (IP) core supports functionality of both the standard physical coding s…
Multi-Rate Ethernet PHY FPGA IP
The Multi-Rate Ethernet PHY FPGA IP core can dynamically support multiple data rates without any design regeneration or device re…
The XAUI PHY Intel® FPGA IP core allows you to easily build systems with a very high throughput 10G Ethernet connection.
GF12 - 0.8V LVDS Rad-Hard Transceiver in GF 12nm
A radiation-hardened GlobalFoundries 12nm LP/LP+ 0.8V LVDS Transceiver.