Crystal-less USB1.1 device PHY(No analog PADs)
IP
- USB 1.1
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
Crystal-less USB1.1 device PHY(No analog PADs)
IP
Crystal-less USB1.1 device PHY
IP
Crystal-less USB2.0 device PHY
IP
Ultra-low cost and high performance crystal-less USB2.0 device PHY
IP
Crystal-less USB2.0 device PHY
IP
Crystal-less USB2.0 device PHY
IP
Crystal-less USB2.0 device PHY
IP
IP
USB 1.1 PHY IP, UMC 0.5um Logic process
USB 1.1 PHY, UMC 0.5um Logic process 3.3V 1P3M.
USB 2.0 Device PHY IP, Non-Crystal mode support, HJTC 0.11um pFlash/LL process
USB2.0 PHY, crystal-less, HJ 0.11um pflash LL process.
USB 1.1.OTG PHY IP, HJTC 0.18um eFlash/G2 process
HJTC 0.18um eFlash process, USB 1.1 OTG.
IP
10-bit dual-port 30MHz ~ 85MHz LVDS Tx;
IP
IP
10/100 Base-TX Fast Ethernet PHY; TSMC 55nm GP
IP
USB 2.0 OTG PHY IP, OTG, UMC 0.153um Logic process
USB OTG 2.0 PHY, UMC 0.153um Logic process.
IP
USB 2.0 HUB - Hub PHY, 1upstream /4 downstream
IP
IP
IP