Overview
Industry 1st Integrated Turnkey Solution for Droop and DVFS Response
Enabling Silicon Monitoring and Health Analytics with Precise Run-Time Droop Response Data
The Aeonic Integrated Droop Response System revolutionizes the way we respond to droop in complex integrated circuits. This innovative solution is designed to simultaneously mitigate voltage droop and enable fine-grained DVFS capability in an integrated turnkey solution, resulting in significant power savings for SoCs.
It also includes extensive observability features that provides valuable insight for modern silicon health and lifecycle management systems. With its fast adaptation time, multi-threshold droop detection, remote/local droop detection support, APB & JTAG interfaces, this system helps architects manage droop and DVFS while generating actionable insights for silicon health and analytics platforms.
Learn more about Power Management Unit IP core
Equips AI and HPC chip designers with on-die power optimization and advanced telemetry IP to unlock next-generation power efficiency.
Today, Movellus is announcing Aeonic Insight PDNIQ 2, a bench-to-in-field telemetry platform for datacenter power management that enables SoCs to run at their true power and performance limits across the full bench-to-in-field cycle.
Movellus announced the inclusion of its clocking technology in the Synopsys Silicon Lifecycle Management (SLM) IP portfolio, directly addressing power challenges facing complex chips in the age of AI. The Synopsys SLM Advanced Clock Generator (“ACG”) IP serves as the foundation for real-time power optimization, enabling power architects to dynamically adapt SoC profiles to environmental and workload changes optimizing performance and power.
Movellus Aeonic Generate™ IP Family Continues Expansion in Defense and Space Applications
Aeonic Insight PDN IQ arms industry with unprecedented transistor-level PDN visibility and analytics that spans the entire product cycle from bench to in-field monitoring
Movellus announced today that RTX’s, SEAKR Engineering, LLC, selected the Aeonic™ Generate Intellectual Property (IP) Platform for its next-generation radiation-tolerant ASIC designs.