Overview
The HCLTech_gf40_gpio_i2c_i3c_bi_3p3v IP is a versatile and robust I3C IO interface designed to facilitate efficient communication in various applications. It is engineered to support both MIPI I3C and I2C protocols across a wide voltage range, making it highly adaptable to different system requirements. This IP ensures high-speed data transfer and reliable operation, even in demanding environments.
The interface is optimized for bi-directional communication and is capable of operating at different voltage levels, providing flexibility for integration into diverse electronic systems. It is designed to handle different I2C modes, ensuring broad compatibility with existing devices and facilitating seamless integration. In addition to its communication capabilities, this IP includes features that enhance its functionality and reliability. It offers programmable options for drive strength, input configurations, and noise immunity, allowing for fine-tuned performance based on specific application needs. Furthermore, it incorporates robust ESD protection to ensure durability and longevity in various operating conditions.
The hcltech_gf40_gpio_i2c_i3c_bi_3p3v IP is a comprehensive solution for implementing I3C and I2C communication in modern electronic systems, providing a blend of high performance, flexibility, and reliability.
Learn more about GPIO IP core
This paper discusses about the low power IP components from ARM can help one to realize the low power features in the SoC. It should be noted that this paper does not discuss about the low power concepts or design techniques. Rather, it focuses on the implementation approaches using ARM low power IP.
For over a decade, Sofics has collaborated with CERN, the European Organization for Nuclear Research. Sofics has delivered advanced GPIO cells tailored for radiation-hardened applications, supporting CERN’s groundbreaking particle physics experiments.
This paper provides a complete solution to the GPIO Verification for any SoC. GPIO interface is available in every ASIC. To avoid duplicate efforts and (save) time to verify the GPIO interface, we have produced this Generic GPIO verification suite. It is a UVM-based verification environment, with all the necessary subcomponents that are required to verify any GPIO design.
Most chips live an easy life with room temperature, clean power and a steady supply. The chips in this article do not. They sit inside nuclear reactors, ride on satellites and work next to particle beams, where a single stray particle can corrupt data or destroy a device.
One of the critical problems in today’s computing is that transporting data can be more costly in energy and time than computing. With the growing complexity of AI models, SoC designers have shifted their focus toward optimizing memory hierarchies, increasing bandwidth in interconnects, and architecting based on workloads for improved efficiency.
To complete our task as engineers we rely on the tools we use. We collaborated with Siemens EDA solutions back in 2025 on a webinar about how we use their tools to develop our designs and layouts.
