Overview
Certus is pleased to offer I2C open-drain IOs across multiple process technologies. The Certus I2C IO can support external supplies of 1.8V, 3.3V and 5V at Fast Mode (400Kbps) and Fast Mode+ (1Mbps) data rates. The Certus solution features power sequence independence, a hysteresis input, and true fail-safe operation. Fully compatible with the Certus GPIO library, this cell can be configured across a broad range of open-drain interfaces, resistive and capacitive loads. Our Open Drain IO solutions are also SMBUS, DDC, CEC and HPD compliant.
Built into our IO libraries, and also offered as a separate service, is our strong ESD expertise. Certus was founded by ESD engineers and our results speak for themselves. Not only do we consistently exceed the standard ESD targets of 2KV HBM and 500V CDM, but we also provide on-chip solutions for standards such as IEC-61000-4-2, system-level ESD and Cable Discharge Events (CDE).
Certus also offers RGMII, Secure Digital, LVDS, Analog/RF, HV and numerous other IO variants across most major foundries and technology nodes. We are particularly suited at providing customized options in a cost-efficient framework. Please contact us for supplementary physical or electrical features that can suit your needs.
Learn more about GPIO IP core
Certus Semiconductor’s I/O libraries for TSMC’s 22nm ultra-low leakage (22ULL) and 22nm ultra-low power (22ULP) technologies offer robust, high-performance solutions tailored to a wide range of SoC designs — from ultra-low power IoT nodes to demanding consumer and automotive systems. Whether you need low leakage, high drive strength, or analog compatibility, our production-proven IP covers it all.
For over a decade, Sofics has collaborated with CERN, the European Organization for Nuclear Research. Sofics has delivered advanced GPIO cells tailored for radiation-hardened applications, supporting CERN’s groundbreaking particle physics experiments.
This paper provides a complete solution to the GPIO Verification for any SoC. GPIO interface is available in every ASIC. To avoid duplicate efforts and (save) time to verify the GPIO interface, we have produced this Generic GPIO verification suite. It is a UVM-based verification environment, with all the necessary subcomponents that are required to verify any GPIO design.
Most chips live an easy life with room temperature, clean power and a steady supply. The chips in this article do not. They sit inside nuclear reactors, ride on satellites and work next to particle beams, where a single stray particle can corrupt data or destroy a device.
One of the critical problems in today’s computing is that transporting data can be more costly in energy and time than computing. With the growing complexity of AI models, SoC designers have shifted their focus toward optimizing memory hierarchies, increasing bandwidth in interconnects, and architecting based on workloads for improved efficiency.
To complete our task as engineers we rely on the tools we use. We collaborated with Siemens EDA solutions back in 2025 on a webinar about how we use their tools to develop our designs and layouts.
