CDM Dependence on Device Capacitance
This blog will focus on what happens during the CDM pulse itself, and will show how the pulse properties change as a function of DUT to Field Plate capacitance.
Vendor:
Certus Semiconductor
Category:
GPIO
Open-drain I2C and SMBUS, DDC, CEC & HPD IO offerings
Certus is pleased to offer I2C open-drain IOs across multiple process technologies.
Overview
Certus is pleased to offer I2C open-drain IOs across multiple process technologies. The Certus I2C IO can support external supplies of 1.8V, 3.3V and 5V at Fast Mode (400Kbps) and Fast Mode+ (1Mbps) data rates. The Certus solution features power sequence independence, a hysteresis input, and true fail-safe operation. Fully compatible with the Certus GPIO library, this cell can be configured across a broad range of open-drain interfaces, resistive and capacitive loads. Our Open Drain IO solutions are also SMBUS, DDC, CEC and HPD compliant.
Built into our IO libraries, and also offered as a separate service, is our strong ESD expertise. Certus was founded by ESD engineers and our results speak for themselves. Not only do we consistently exceed the standard ESD targets of 2KV HBM and 500V CDM, but we also provide on-chip solutions for standards such as IEC-61000-4-2, system-level ESD and Cable Discharge Events (CDE).
Certus also offers RGMII, Secure Digital, LVDS, Analog/RF, HV and numerous other IO variants across most major foundries and technology nodes. We are particularly suited at providing customized options in a cost-efficient framework. Please contact us for supplementary physical or electrical features that can suit your needs.
Built into our IO libraries, and also offered as a separate service, is our strong ESD expertise. Certus was founded by ESD engineers and our results speak for themselves. Not only do we consistently exceed the standard ESD targets of 2KV HBM and 500V CDM, but we also provide on-chip solutions for standards such as IEC-61000-4-2, system-level ESD and Cable Discharge Events (CDE).
Certus also offers RGMII, Secure Digital, LVDS, Analog/RF, HV and numerous other IO variants across most major foundries and technology nodes. We are particularly suited at providing customized options in a cost-efficient framework. Please contact us for supplementary physical or electrical features that can suit your needs.
Key features
- I2C Open-drain
- Fast mode (400kbps) and Fast mode+ (1Mbps) data rates
- 1.8V - 5V external supply tolerant
- Output Enable
- Hysteresis receiver
- External resistor support of 1K-Ohm to 50K-Ohm
- Full interoperability with Certus GPIO library
- Power sequence independence
- ESD protection of 2KV HBM, 500V CDM
- Physical Features
- Flexible cell and pad arrangements
- Wirebond and Flip-chip support
- Metal stack variants
Block Diagram
Certus I2C block diagram
Benefits
- Fast Mode and Fast Mode+ data rates
- 1.8V - 5V external supply
- External resistor support of 1K-Ohm to 50K-Ohm
- Hysteresis receiver
- Interoperability with Certus GPIO libraries
- Flexible cell and pad arrangements
- Wirebond & Flip-chip support
- Metal stack variants
- Power sequence independence
- Proven >2KV HBM / 500V CDM ESD protection
Applications
- I2C, SMBUS, DDC, CEC, HPD
What’s Included?
- GDS
- CDL netlist
- Verilog stub
- Verilog behavioral model
- LEF
- Liberty Timing Files
- IBIS (option)
- Electrical datasheet
- User guide and application notes
- Consulting and Support
Specifications
Identity
Part Number
Certus I2C
Vendor
Certus Semiconductor
Type
Silicon IP
Provider
HQ:
United States
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Frequently asked questions about GPIO Pad Library IP cores
What is Open-drain I2C and SMBUS, DDC, CEC & HPD IO offerings?
Open-drain I2C and SMBUS, DDC, CEC & HPD IO offerings is a GPIO IP core from Certus Semiconductor listed on Semi IP Hub.
How should engineers evaluate this GPIO?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this GPIO IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.