HDMI2.1/2.0/1.4 TX and RX PHY & Controller

The HDMI IP is designed for transmitting or receiving video and audio signals between the video source devices and display devices. It is fully compliant with HDMI2.1, 2.0, 1.4 and DVI 1.0 specifications. The IP provides both PHY and controller solutions, offering a reliable implementation for HDMI interfaces that can be seamlessly integrated into the SoCs used in multimedia devices.

The HDMI Transmitter integrates four data channels, a low-jitter PLL, and a bias circuit to deliver high-quality multimedia data. The controller receives video, audio, synchronization signals, and control signals from SoC logic. These signals are merged, scrambled and encoded by the controller for transmission.

The HDMI Receiver separates the incoming data stream into audio data, video data, and packet data information. The video interface supports a variety of video formats including RGB444, YUV444, YUV422, and YUV420. The audio interface includes up to four I2S outputs, SPDIF outputs and a parallel audio output, providing comprehensive support for HDMI audio formats.

• Compliant with HDMI2.1, HDMI2.0, HDMI1.4, and DVI1.0 specifications
• Supports data rate up to 12Gbps per data channel and 8k60 resolution
• Supports TMDS mode and FRL mode with 3-lane or 4-lane configuration
• Supports RGB444 and YCbCr444/422/420 video formats with 8/10/12-bit color depth
• Supports 8-ch I2S and 2-ch S/PDIF audio interface with sampling rate up to 192KHz
• Supports HDCP1.4, HDCP2.2 and HDCP2.3
• Supports DSC1.2a
• Supports eARC/ARC
• Supports programmable termination, swing and equalization
• Supports SSC modulation
• Supports BIST and Loopback
• Supports APB slave interface for internal register access
• Built-in low jitter PLL and bandgap reference
• The area and power consumption correlate strongly with process node, please refer to detailed datasheet

• Low power consumption
• Fully customizable
• Small area
• Simple integration process
• Available options include
  • Test chips and test boards
  • FPGA integration support
  • Chip level integration

• Datasheet
• Physical Integration Guide
• Timing Library Model (LIB)
• Encrypted Verilog Model
• Library Exchange Format (LEF)
• GDSII Database
• Evaluation Board if Available