HD Multi-window Video Processor IP Core

This brief specification describes the operation of the HD Multi-window Video Processor (evaluation) IP Core. The IP Core is provided as a netlist in either EDIF, Verilog or VHDL formats.

The evaluation demo accepts 4 x standard HD720p60 video inputs and 1 x video output comprised of 24-bit RGB 8:8:8 pixel data, vsync, hsync, data enable and a 74.25 MHz pixel clock. The four video inputs are scaled-down into four separate video windows to present a quad-tiled display. The demo also generates a text overlay in the corner of each tiled window (Window1, Window2, Window3, etc ..) and a 50% alpha blended image that reads ‘ ZIPcores demo’ in the bottom right tile.

In addition, the IP Core requires a simple generic memory interface to allow the incoming video streams to be buffered in an external DDR3 memory. The only other signals necessary are a 150 MHz system clock and a system reset. All clock signals are asynchronous relative to each other. Any minor differences in frequency and/or phase are controlled by the internal frame buffer. The photo on the following page demonstrates a typical bench setup with the output video driving a standard COTS monitor via the HDMI port.