Vendor: Techno Mathematical Co., Ltd. Category: Video Processing

H.265/HEVC 422 10bit Decoder for 4K

Support up to 4K60fps processing

H.265 / HEVC View all specifications

Overview

H.265/HEVC is a video compression/decompression standard that has been standardized by ISO/IEC. H.265/HEVC, which has a higher compression ratio compare to the current mainstream MPEG2 or H.264/AVC, is expected to become the standard for 4K (3840×2160 pixels) TV broadcasting, which has four times the number of pixels of Full HD that is widely used in ordinary TVs, as well as for high-definition video distribution and video services for mobile devices with limited bandwidth. There are high expectations for H.265/HEVC.

TMC has developed a compact, low-power encoder/decoder that maintains high image quality and performance.

Specification

Supported Standards Compliant to ISO/IEC23008-2, ITU-T Rec. H.265 standard
Maximum Performance 4K60fps
Image Format YCbCr 4:2:0 / 4:2:2
Image Bit Depth 8 / 10 bits
Output Format Byte stream format (Annex B)
External Memory Interface AXI4

This IP supports both color spaces of YCbCr and YUV.

Key features

  • Support up to 4K60fps processing
  • Up to 4K30fps processing is possible on FPGA. (e.g. Arria10 series, Kintex Ultrascale(+) series, with support for devices from Lattice, Efinix, and Microchip)
  • The AXI Bus is equipped as standard for external memory access for easy integration.
  • Based on elemental technologies that have been used in digital cameras for many years, we have successful results in high image quality and low power consumption.

Block Diagram

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Specifications

Identity

Part Number
TM24726
Vendor
Techno Mathematical Co., Ltd.
Type
Silicon IP

Compute

Codec Standard
H.265 / HEVC

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Learn more about Video Processing IP core

Picking the right MPSoC-based video architecture: Part 1

A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing

Analysis: ARC's Configurable Video Subsystems

Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.

Frequently asked questions about Video Processing IP

What is H.265/HEVC 422 10bit Decoder for 4K?

H.265/HEVC 422 10bit Decoder for 4K is a Video Processing IP core from Techno Mathematical Co., Ltd. listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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