Vendor: VISENGI Category: Video Processing

H.264 Encoder High Profile (8K on Zynq/Arria)

VISENGI's H.264 Encoder IP core has been developed to be the highest throughput standards compliant hardware H.264 video compress…

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H.264 / AVC View all specifications

Overview

VISENGI's H.264 Encoder IP core has been developed to be the highest throughput standards compliant hardware H.264 video compressor. VISENGI offers two encoder variants to meet the different targets of features, resource usage, and compression:

• H264E-P: H.264 encoder compliant with High 4:4:4 Predictive Profile: the IP core is larger but offers a significantly better compression


• H264E-I: H.264 encoder compliant with CAVLC 4:4:4 Intra Profile (all frames are keyframes): the IP core is smaller but yields less compression. It does not require external memory.


Both share the same outstanding processing speed of more than 5.2 pixels encoded per cycle.

Achieves UltraHD on mid-range and low-cost Spartan-6/Cyclone III FPGAs. 4K 60 on Artix-7 and Cyclone V. 8K30 on Arria 10 and Zynq 7030.

Key features

  • Video compression standard ITU.T Rec. H.264 | ISO/IEC 14496-10 AVC.
  • EXTREME SPEED, providing a constant throughput of 5.2 pixels encoded per clock cycle.
  • Achieves 8K30 on mid-range Zynq-7030 and Arria 10 FPGAs
  • Achieves UltraHD 4K on low-end and low-cost Spartan/Cyclone FPGAs
  • Realtime configurable VBR/CBR mode (Variable/Constant Bit Rate) automatically controls all H.264 parameters.
  • Very low latency (just 16 lines' time).
  • High 4:4:4 Predictive Profile (H264E-P) and CAVLC 4:4:4 Intra Profile (H264E-I and H264E-P).
  • Highest level (5.2) of resolutions and frames per second allowed by H.264 standard attained at just 102 MHz (most low-range FPGAs).
  • Preserves full color fidelity with color subsampling 4:4:4.
  • Selectable number of predicted frames (P) per keyframe (I) on H264E-P.
  • Output in Byte stream format (raw .264) for easier encapsulation.
  • (H264E-P) Full reconstructed video preview output.
  • (H264E-I) Optional pseudo-reconstructed video preview output.
  • Industry standard interfaces: AXI-Lite slave for configuration/status and AXI3/4 master for pixel-input/encoded-output.
  • Embedded DMA engines in AXI3/4 interfaces for direct connection to a memory controller. Support for high latency memories.
  • Optional AXI4-Stream Pixel-Input and Encoded-Output interfaces.
  • Optional optimized pixel input mode to boost shared memory efficiency.

Block Diagram

H264 High Profile Encoder (8K30 on FPGA) block diagram

What’s Included?

  • Technical support via email
  • IP Core Datasheet
  • Xilinx Vivado drag'n'drop instance
  • Altera Qsys drag'n'drop instance
  • Linux driver for embedded setups
  • Example SW control application

Specifications

Identity

Part Number
H264 High Profile Encoder (8K30 on FPGA)
Vendor
VISENGI
Type
Silicon IP

Compute

Codec Standard
H.264 / AVC

Videos

This is the most "interactive demo", with which you can encode your own PC/video-player (attached to DVI input) and see the resulting H264 encoded + decoded stream on the DVI video output (a screen) in realtime. It also allows uploading encoded videos
This is the most "interactive demo", with which you can encode your own PC/video-player (attached to DVI input) and see the resulting H264 encoded + decoded stream on the DVI video output (a screen) in realtime. It also allows uploading encoded videos to a PC. It includes a small Windows app that allows to remotely control and monitor the encoding, a really visual way to evaluate the compression and quality.

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

VISENGI
HQ: Spain
Contact VISENGI

Learn more about Video Processing IP core

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A look at the design of multiprocessor systems-on-chips (MPSoCs) for video applications and how to optimize them for computational power and real-time performance as well as flexibility. Part 1: Architectural approaches to video processing

Analysis: ARC's Configurable Video Subsystems

Adding to its growing portfolio of licensable silicon IP subsystems, ARC has announced five configurable video processing subsystems. The subsystems range from the smallest-size AV 402V to the highest-performance AV 417V, and support multi-standard video encoding and decoding at resolutions ranging from CIF to D1.

Frequently asked questions about Video Processing IP

What is H.264 Encoder High Profile (8K on Zynq/Arria)?

H.264 Encoder High Profile (8K on Zynq/Arria) is a Video Processing IP core from VISENGI listed on Semi IP Hub.

How should engineers evaluate this Video Processing?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Video Processing IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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