Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vendor:
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Category:
SRAM
GSMC 0.18umLP Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler
VeriSilicon GSMC 0.18um High-Speed Synchronous IBLP Memory Compiler optimized for Grace Semiconductor Manufacturing Corporation (…
Overview
VeriSilicon GSMC 0.18um High-Speed Synchronous IBLP Memory Compiler optimized for Grace Semiconductor Manufacturing Corporation (GSMC) 0.18um Logic 1P6M Industry Baseline Low Power Salicide 1.8/3.3V Process can flexibly generate memory blocks via a friendly GUI or shell commands.
The compiler supports a comprehensive range of word and bit lengths. While satisfying speed and power requirements, it is optimized for area efficiency.
VeriSilicon GSMC Synchronous Memory Compiler uses four layers within the blocks and supports metal 4, 5, or 6 as the top metal. Dummy bit cells are synthesized with the intention to enhance reliability
The compiler supports a comprehensive range of word and bit lengths. While satisfying speed and power requirements, it is optimized for area efficiency.
VeriSilicon GSMC Synchronous Memory Compiler uses four layers within the blocks and supports metal 4, 5, or 6 as the top metal. Dummy bit cells are synthesized with the intention to enhance reliability
Key features
- Low Leakage
- High Density
- High Speed
- Size Sensitive Self-Time Delay for Fast Access
- Automatic Power Down
- Tri-State Output(SRAM only)
- Write Mask Function(SRAM & Register File)
Specifications
Identity
Part Number
GSMC18 IBLP MC
Vendor
VeriSilicon Microelectronics (Shanghai) Co., Ltd.
Type
Silicon IP
Provider
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Frequently asked questions about SRAM IP cores
What is GSMC 0.18umLP Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler?
GSMC 0.18umLP Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler is a SRAM IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.