Overview
The present IP is a Voltage Detector (VDT) circuit. When the voltage is in the range of VTHL to VTHH, the output, OUT_RD, is generated as a high level signal. When the voltage is lower than VTHL or higher than VTHH, the output, OUT_RD, is generated as a low level signal. When MODE is set to high, the voltage of VIN is detected. When MODE is set to low, the analog power V33 is detected. This IP cannot operate stand-alone because it needs 1.17V reference voltage and 1.5uA bias current from VeriSilicon GSMC18_PRG_03. And the output OUT_RD may be at uncertain stage during the power-up course before the reference voltage and bias current become stable.
Learn more about Voltage Monitor IP core
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