Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
VeriSilicon CHRT 0.13um High-Speed Synchronous Memory Compiler optimized for Global Foundry 0.13um Logic 1P9M Salicide 1.2/2.5(3.…
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| GlobalFoundries | 130nm | BCD | Silicon Proven |
GF 0.13um Single-Port/Dual-Port SRAM, Single-Port/Two-Port Register File and Diffusion ROM Compiler is a SRAM IP core from VeriSilicon Microelectronics (Shanghai) Co., Ltd. listed on Semi IP Hub. It is listed with support for globalfoundries Silicon Proven.
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