Vendor: Engineering Physics Center of MSU Category: PLL

Fully Digital Glitch Free PLL TSMC 16FFC 16 nm - 300-3000 MHz

A programmable fully digital PLL designed to lock to an incoming clock source and produce an output clock.

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TSMC 16nm FFC Pre-Silicon View all specifications

Overview

A programmable fully digital PLL designed to lock to an incoming clock source and produce an output clock. It is ideal as a clock generator for digital designs, but not intended for analog blocks like ADC/DAC or SERDES clocking. This digital PLL has ultra-low area and low implementation charges due to predictable digital design.

Key features

  • Ideal as a clock generator for digital design
  • Excellent frequency jitter performance
  • Ultra-low area fully digital PLL design
  • Patented glitch free frequency adjustment
  • Fine frequency precision with fractional divider
  • Low implementation charges due to predictable digital design
  • Can be implemented on all modern TSMC processes (HPC+ 28 nm, 16FFC 16 nm, N7+ 7 nm)

Block Diagram

EPC FDPLL16FFC 16 nm block diagram

Benefits

  • Fully digital PLL design
  • Low implementation charges due to predictable digital design
  • Low complexity
  • Competitive price

Applications

  • It is ideal as a clock generator for digital designs, but not intended for analog blocks like ADC/DAC or SERDES clocking. For example, SoC prototypes for mobile applications and IoT.

What’s Included?

  • GDSII (100% DRC and LVS clean)
  • Verilog model
  • LEF
  • User integration Guidelines

Silicon Options

Foundry Node Process Maturity
TSMC 16nm FFC Pre-Silicon

Specifications

Identity

Part Number
EPC FDPLL16FFC 16 nm
Vendor
Engineering Physics Center of MSU
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Engineering Physics Center of MSU
HQ: Russian Federation
Contact Engineering Physics Center of MSU

Learn more about PLL IP core

Creating a Frequency Plan for a System using a PLL

How do you ensure that every part of a system receives the clock it needs—without wasting power or sacrificing performance? The answer lies in creating a well-structured frequency plan built around a PLL.

Specifying a PLL Part 3: Jitter Budgeting for Synthesis

This white paper is aimed at system architects and physical implementation leaders working on the design of SoCs. It can be confusing to understand the impact of different jitter sources and how to calculate a jitter budget when specifying a digital system. This white paper explains how jitter changes the period of a clock and how to ensure that jitter has correctly been accounted for in the calculations for timing closure.

Specifying a PLL Part 2: Jitter Basics

This article explains a some of the key terminology and parameters commonly used to describe jitter. It will also help clarify the most important parameters for a some PLL applications, allowing the designer to better understand what is required from a PLL.

Specifying a PLL Part 1: Calculating PLL Clock Spur Requirements from ADC or DAC SFDR

In high end RF systems, such as 5G radios, the requirements are so stringent that the source of this strongest unwanted tone can be the PLL. This article outlines how spurs in the input clock to the ADC or DAC may limit the SFDR. This in turn will set the requirements for the spurs for the input clock (from a PLL), in order to achieve a specific SFDR.

Achieving Groundbreaking Performance with a Digital PLL

This article compares analog, first-generation digital, and second-generation digital PLLs. It evaluates which type of PLL may be best in which situation. It further discloses a roadmap into other application areas, including general purpose / logic clocking, and regular low-jitter PLLs.

Frequently asked questions about PLL IP cores

What is Fully Digital Glitch Free PLL TSMC 16FFC 16 nm - 300-3000 MHz?

Fully Digital Glitch Free PLL TSMC 16FFC 16 nm - 300-3000 MHz is a PLL IP core from Engineering Physics Center of MSU listed on Semi IP Hub. It is listed with support for tsmc Pre-Silicon.

How should engineers evaluate this PLL?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this PLL IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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