Vendor: SmartDV Category: SRAM

FPMRAM Memory Model

FPMRAM Memory Model provides an smart way to verify the FPMRAM component of a SOC or a ASIC.

Overview

FPMRAM Memory Model provides an smart way to verify the FPMRAM component of a SOC or a ASIC. The SmartDV's FPMRAM memory model is fully compliant with standard FPMRAM Specification and provides the following features. Better than Denali Memory Models.

FPMRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

FPMRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Supports FPMRAM memory devices from all leading vendors.
  • Supports 100% of FPMRAM protocol standard.
  • Supports all the FPMRAM commands as per the specs.
  • Supports up to 16 MB device density.
  • Supports the X16 device mode operation.
  • Checks for following
    • Check-points include power up, initialization and power off rules
    • State based rules, Active Command rules
    • Read/Write Command rules etc.,
    • All timing violations
  • Supports for Byte Write and Byte Read operation via two CAS.
  • Supports following refresh intervals.
    • 512 cycles/8ms
    • 1024 cycles/16ms
  • Supports for following Refresh Mode:
    • RAS-Only
    • CAS-before-RAS (CBR)
    • Hidden
  • Supports for full-timing as well as behavioral versions in one model.
  • Supports for all timing delay ranges in one model: min, typical and max.
  • Quickly validates the implementation of the standard FPMRAM specification.
  • Protocol checker fully compliant with FPMRAM Specification.
  • Constantly monitors FPMRAM behavior during simulation.
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
  • Built in functional coverage analysis.
  • Supports Callbacks, so that user can access the data observed by monitor.

Block Diagram

FPMRAM Memory Model block diagram

Benefits

  • Faster testbench development and more complete verification of FPMRAM designs.
  • Easy to use command interface simplifies monitor control and configuration.
  • Simplifies results analysis.
  • Runs in every major simulation environment.

What’s Included?

  • Complete regression suite containing all the FPMRAM testcases.
  • Examples showing how to connect and usage of Model.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
FPMRAM Memory Model
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about SRAM IP core

Keeping Pace with CXL Specification Revisions

As the Compute Express Link® (CXL®) specification rapidly evolves, so too must the tools and infrastructure used to verify designs built around it. Maintaining verification IP (VIP) that keeps pace with new specification revisions is no small task, particularly when dealing with major version shifts like the transition from CXL 2.0 to 3.0.

SmartDV Licenses SDIO IP Family to Ranix for V2X Products

To meet RANiX’s unique design goals, SmartDV will customize the IP to go beyond the standard SDIO functionality—thereby empowering RANiX to differentiate from their competitors. SmartDV will also provide RANiX with the requisite support and documentation to achieve ASIL certification for ISO 26262.

SmartDV Rolls Out Multi-Phase Expansion Plan

SmartDV™ Technologies, provider of flexible, customizable semiconductor design IP (intellectual property) and verification solutions, has expanded engineering operations beyond its headquarters in Bengaluru with the opening of a new office space in Coimbatore, Tamil Nadu, India.

Frequently asked questions about SRAM IP cores

What is FPMRAM Memory Model?

FPMRAM Memory Model is a SRAM IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this SRAM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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