Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vendor:
SmartDV Technologies
Category:
SRAM
FPMRAM Memory Model
FPMRAM Memory Model provides an smart way to verify the FPMRAM component of a SOC or a ASIC.
Overview
FPMRAM Memory Model provides an smart way to verify the FPMRAM component of a SOC or a ASIC. The SmartDV's FPMRAM memory model is fully compliant with standard FPMRAM Specification and provides the following features. Better than Denali Memory Models.
FPMRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
FPMRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Key features
- Supports FPMRAM memory devices from all leading vendors.
- Supports 100% of FPMRAM protocol standard.
- Supports all the FPMRAM commands as per the specs.
- Supports up to 16 MB device density.
- Supports the X16 device mode operation.
- Checks for following
- Check-points include power up, initialization and power off rules
- State based rules, Active Command rules
- Read/Write Command rules etc.,
- All timing violations
- Supports for Byte Write and Byte Read operation via two CAS.
- Supports following refresh intervals.
- 512 cycles/8ms
- 1024 cycles/16ms
- Supports for following Refresh Mode:
- RAS-Only
- CAS-before-RAS (CBR)
- Hidden
- Supports for full-timing as well as behavioral versions in one model.
- Supports for all timing delay ranges in one model: min, typical and max.
- Quickly validates the implementation of the standard FPMRAM specification.
- Protocol checker fully compliant with FPMRAM Specification.
- Constantly monitors FPMRAM behavior during simulation.
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
- Built in functional coverage analysis.
- Supports Callbacks, so that user can access the data observed by monitor.
Block Diagram
FPMRAM Memory Model block diagram
Benefits
- Faster testbench development and more complete verification of FPMRAM designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
What’s Included?
- Complete regression suite containing all the FPMRAM testcases.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
Specifications
Identity
Part Number
FPMRAM Memory Model
Vendor
SmartDV Technologies
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
India
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Frequently asked questions about SRAM IP cores
What is FPMRAM Memory Model?
FPMRAM Memory Model is a SRAM IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.