Dual Port SRAM Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/LL fusion (FSG) process high density synchronous high density Dual Port (2RW) SRAM memory compiler.
Dual Port SRAM Compiler IP, UMC 0.13um SP/FSG process
UMC 0.13um SP/FSG Logic process high density synchronous high density Dual Port (2RW) SRAM memory compiler.
SATA II PHY IP, Support SATA Gen1 1.5Gb/s and SATA Gen2 3.0Gb/s, UMC 0.18um Logic process
Single channel serial ATA PHY layer compliant with SATA spec.
ROM Compiler IP, UMC 0.15um SP process
UMC 0.15um SP Logic process synchronous VIA2 programmed ROM memory compiler.
D/A Converter IP, 16 bits, 96Ksps, UMC 0.18um G2 process
16-Bit 96KSPS voltage output stereo-line Digital-to-Analog converter, UMC 0.18um GII Logic process.
10-Bit 44MSPS dual channel differential current output Digital-to-Analog converter, UMC 0.18um GII Logic process.
Standard Cell (Generic) Library IP, 8 tracks, UMC 0.13um SP/FSG process
UMC 0.13um SP/FSG Logic process high density Core Cell Library.
Specialty PCI IO IP, UMC 0.15um SP process
UMC 0.15um SP process true 3.3V PCI IO cells.
Specialty OSC IO IP, UMC 0.15um SP process
UMC 0.15um SP process true 1.5V Oscillator IO cells.
Multi-Voltage IO IP, BOAC (Bonding Over Active Circuit), UMC 0.15um SP process
UMC 0.15um SP process standard Multi-Voltage IO.
Standard Cell (Generic) Library IP, 9 tracks, UMC 0.15um SP process
UMC 0.15um SP Logic process standard Core Cell Library.
Specialty PCI IO IP, 5V tolerance, UMC 0.15um SP process
UMC 0.15um SP process 5.0V tolerant PCI 33/66 IO cells.
Multi-Voltage IO IP, BOAC (Bonding Over Active Circuit), UMC 0.18um LL process
UMC 0.18um LL Logic process standard Multi-Voltage IO.
Specialty SSTL IO IP, UMC 0.25um Logic process
UMC 0.25um Logic process true 2.5V SSTL2 IO cells.
Specialty PCI IO IP, 5V tolerance, UMC 0.25um Logic process
UMC 0.25um Logic process 5.0V tolerant PCI IO cells.
Single Port SRAM Compiler IP, UMC 0.15um SP process
UMC 0.15um SP Logic process synchronousultra high speed Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, 4.0um2 bit cells, Synchronous high density, UMC 0.18um LL process
UMC 0.18um LL Logic process synchronous high density Single Port SRAM memory compiler.
A/D Converter IP, 10 bits, 400Ksps, UMC 0.25um Logic process
10-Bit 400KSPS single-end Analog-to-Digital converter, UMC 0.25um Logic process.
A/D Converter IP, 10 bits, 40Msps, UMC 0.18um Mixed-Mode process
10-Bit 40MSPS Differential Analog-to-Digital converter, UMC 0.18um Mixed-Mode process.
Voltage Detector IP, 3 Levels, UMC 0.18um G2 process
3-level detector for MMC flash storage, VCCA=3.3V, Ivcca=65uA, UMC 0.18um GII Logic process.