RC Oscillator IP, Output: 4MHz - 15MHz, UMC 0.13um HS/FSG process
4M~15MHz RC Oscillator with External R, UMC 0.13um HS/FSG Logic process.
- UMC
- 130nm
- HS
RC Oscillator IP, Output: 4MHz - 15MHz, UMC 0.13um HS/FSG process
4M~15MHz RC Oscillator with External R, UMC 0.13um HS/FSG Logic process.
Input 20M-200MHz, output 250M-500MHz, frequency synthesizable PLL, UMC 0.13um Logic HS process.
PLL IP, Input: 20MHz - 200MHz, Output: 250MHz - 500MHz, UMC 0.13um HS/FSG process
The FXPLL130HC0H is a phase locked loop with an operating range of 250M~500MHz, UMC 0.13um HS/FSG Logic process.
Input 20M-200MHz, output 500M-1000MHz, frequency synthesizable PLL, UMC 0.13um Logic HS process.
Input 20M-200MHz, output 50M-100MHz, frequency synthesizable PLL, UMC 0.13um Logic HS process.
Audio ADDA IP, 18 bits, 96KHz, UMC 0.25um Logic process
18-Bit 96KHz Sigma-Delta audio Codec, UMC 0.25um Logic process.
Audio ADDA IP, 18 bits, 96KHz, UMC 0.25um Logic process
18-Bit 96KHz Sigma-Delta audio Codec, UMC 0.25um Logic process.
Specialty PCI IO IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process true 3.3V PCI IO cells.
Specialty PECL IO IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process Low Voltage true 3.3V PECL IO cells.
Specialty SSTL IO IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process true 2.5V SSTL2 IO cells.
General Purpose Multi-Voltage IO IP, 1.8V/2.5V/3.3V Operations, UMC 0.18um G2 process
UMC 0.18um GII Logic process standard Multi-Voltage IO.
Linear Regulator IP, Output: 3.3V/240mA, UMC 0.18um LL process
3.3V with 240mA driving capability, Istb=uA Linear Regulator, UMC 0.18um LL Logic process.
Voltage Detector IP, UMC 0.18um LL process
Voltage detector for flash protect, UMC 0.18um LL Logic process.
Voltage Detector IP, UMC 0.18um LL process
VDT for MMC, UMC 0.18um LL Logic process.
Band Gap IP, Input: 1.0V - 1.8V, VBG=0.615V, UMC 0.18um LL process
VBG=0.615V, VCCA=1.8V, VCCA_min=1.0V, Ivcca=23uA, UMC 0.18um LL Logic process.
Linear Regulator IP, Output: 3.3V/100mA, UMC 0.15um SP process
3.3V with 100mA driving capability, Istb=65uA Linear Regulator, UMC 0.15um SP Logic process.
Two Port Register File Compiler IP, UMC 0.13um SP/FSG process
UMC 0.13um SP/FSG Logic process synchronous Two Port (1R1W) Register File SRAM memory compiler.
One Port Register File Compiler IP, UMC 0.13um SP/FSG process
UMC 0.13um SP/FSG Logic process high density synchronous Single Port Register File SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/LL fusion (FSG) process high density synchronous high density Single Port SRAM memory compiler.
Single Port SRAM Compiler IP, UMC 0.13um SP/FSG process
UMC 0.13um SP/FSG Logic process high density synchronous high density Single Port SRAM memory compiler.