UMC IP Cores

UMC 65nm standard performance Logic process synchronous extra high speed Single Port SRAM memory compiler.

• UMC
• 65nm

UMC 65nm standard performance process synchronous high density Single Port Register File SRAM memory compiler.

• UMC
• 65nm

UMC 65nm SPRVT Logic process synchronous VIA1 ROM memory compiler.

• UMC
• 65nm

UMC 65nm SP/RVT Logic and HVT Low-K process synchronous, high density, Dual Port SRAM compiler with the row redundancy option.

• UMC
• 65nm

DC-DC Power converter, Input:3.0V~3.6V, output:5V, 50mA loading, UMC 65nm LL/RVT Low_K process.

• UMC
• 65nm
• LL

Input 20M-200MHz, output 300M-600MHz, frequency synthesizable PLL, UMC 65nm LL Logic/RVT Low-K process.

• UMC
• 65nm
• LL

Input 5M-500MHz, output 31.25M-500MHz, frequency synthesizable PLL, UMC 65nm SP/RVT process.

• UMC
• 65nm

UMC 0.11um CMOS Image Sensor 2P3M process synchronous high density Single Port Register File SRAM memory compiler.

• UMC
• 110nm

UMC 90nm LL Logic-HVT process standard Core Cell Library.

• UMC
• 90nm
• LL

Input 1.0V-1.5V, VBG=0.615V, Bnad Gap, HS process, UMC 0.13um HS/FSG Logic process.

• UMC
• 130nm
• HS

3.3V to 1.2V, 1.0V and 0.8V with 50mA driving capability for each, Istb=130uA, Linear Regulator.

• UMC
• 130nm
• HS

USB 2.0 On-The-Go PHY, UMC 0.13um LL process.

• USB 2.0
• UMC
• 130nm
• LL

UMC 0.11um LL Logic/FSG process 3.3V low frequency crystal osc.

• UMC
• 110nm
• LL

UMC 0.11um LL Logic/FSG process 3.3V high frequency crystal osc.

• UMC
• 110nm
• LL

UMC 0.11um LL Logic process true 3.3V Analog ESD IO.

• UMC
• 110nm
• LL

UMC 0.11um HS/FSG Logic process 3.3V low frequency crystal osc.

• UMC
• 110nm
• HS

UMC 0.11um SP/FSG Logic process 3.3V low frequency crystal osc.

• UMC
• 110nm
• SP

UMC 0.11um SP/FSG Logic process 3.3V high frequency crystal osc.

• UMC
• 110nm
• SP

UMC 0.11um SP Logic process true 3.3V Analog ESD IO.

• UMC
• 110nm
• HS

UMC 0.11um HS/FSG Logic process 3.3V high frequency crystal osc.

• UMC
• 110nm
• HS