USB 2.0 OTG PHY IP, UMC 55nm LP process
USB2.0 OTG PHY (VDT and ID are included in PHY), UMC 55nm LP Low-K Logic process.
- USB 2.0
- UMC
- 55nm
- LP
USB 2.0 OTG PHY IP, UMC 55nm LP process
USB2.0 OTG PHY (VDT and ID are included in PHY), UMC 55nm LP Low-K Logic process.
USB 1.1.OTG PHY IP, OTG, UMC 0.11um HS/AE process
USB1.1 PHY feature USB 1.1 On-The-Go PHY, UMC 0.11um HS/AE (AL Enhancement) Logic process.
USB 2.0 Device PHY IP, Non-Crystal mode support, UMC 0.11um HS/AE process
Crystal-Less USB2.0 PHY, UMC 0.11um HS/AE (AL Enhancement) Logic process.
USB 1.1 PHY IP, UMC 0.13um LL/FSG process
USB 1.1 transceiver, UMC 0.13um LL Logic/FSG process.
SATA III PHY IP, Gen-3, UMC 55nm SP process
Serial ATA I, II, III PHY, UMC 55nm SP/RVT Low-K Logic process.
SATA III PHY IP, Gen-3, UMC 0.11um HS/FSG process
6G/3G/1.5G Serial ATA PHY, UMC 0.11um HS/FSG Logic process.
PCI Express PHY IP, PCIe Gen-1, 1 Lanes, UMC 0.13um HS/FSG process
PCI-Express PHY with PIPE interface, 1 lane PCI-E PHY with Low Power feature, UMC 0.13um HS/FSG Logic process.
MIPI D-PHY Transmitter IP, 80Mbps - 1.5Gbps, UMC 55nm SP process
MIPI Transmitter 80~1500MHz, UMC 55nm SP/RVT Low-K Logic process.
MIPI D-PHY Receiver IP, 80Mbps - 1.5Gbps, UMC 55nm SP process
MIPI Receiver 80~1500MHz, UMC 55nm SP/RVT Low-K Logic process.
MIPI D-PHY Transmitter IP, 80Mbps - 1Gbps, UMC 40nm LP process
MIPI Transmitter 80~1000MHz, UMC 40nm LP/RVT Low-K process.
MIPI D-PHY Receiver IP, 80Mbps - 1Gbps, UMC 40nm LP process
MIPI Receiver 80Mbps-1Gbps, Combo PHY for MIPI & HiSPi & LVDS & SubLVDS, UMC 40nm LP Low-K Logic process, Two Lane.
MIPI D-PHY Receiver IP, 80Mbps - 1Gbps, UMC 40nm LP process
MIPI Receiver 80Mbps-1Gbps, Combo PHY for MIPI & HiSPi & LVDS & SubLVDS, UMC 40nm LP Low-K Logic process.
MIPI D-PHY Receiver IP, 80Mbps - 1Gbps, UMC 40nm LP process
MIPI Receiver 80Mbps-1Gbps, UMC 40nm LP Low-K Logic process.
Band Gap IP, Input: 3V - 3.6V, VBG=1.22V, UMC 55nm SP process
Input 3V-3.6V, VBG=1.22V, bandgap, UMC 55nm SP/RVT Low-K Logic process.
Band Gap IP, Input: 3.3V, VBG=880.3 mV, UMC 55nm SP process
Power input 3.3V, VBG=880.3 mV bandgap, UMC 55nm SP/RVT Low-K process.
Band Gap IP, Input: 2V - 3.6V, VBG=1.2V, UMC 65nm LP process
Input 2V-3.6V, VBG=1.2V, Band Gap, UMC 65nm LP/RVT Low-K Logic process UHS Library.
Band Gap IP, Input: 2V - 3.6V, VBG=1.23V, UMC 40nm LP process
Input 2V-3.6V, VBG=1.23V bandgap, UMC 40nm LP/RVT Low-K Logic process.
Band Gap IP, Input: 2V - 3.6V, VBG=1.207V, UMC 0.11um HS/AE process
Input 2V-3.6V, VBG=1.207V bandgap, UMC 0.11um HS/AE (AL Enhancement) Logic process.
Band Gap IP, Input: 2V - 3.6V, VBG=1.23V, UMC 90nm SP process
Input 2-3.6V, VBG=1.23V, Bnad Gap, UMC 90nm SP/RVT (FSG) Logic process.
Band Gap IP, Input: 2.25V - 2.75V, VBG=1.23V, UMC 65nm LL process
Input 2.25V-2.75V, VBG=1.23V, Band Gap, LL process, UMC 65nm LL/RVT Low-K Logic process.