General Purpose IO IP, UMC 0.13um LL/FSG process
UMC 0.13um Generic process True 3.3V Generic IO.
- UMC
- 130nm
- LL
General Purpose IO IP, UMC 0.13um LL/FSG process
UMC 0.13um Generic process True 3.3V Generic IO.
General Purpose IO IP, 5V tolerance, UMC 0.13um LL/FSG process
UMC 0.13um Generic process 5V Tolerance IO.
General Purpose IO IP, UMC 0.11um LL/FSG process
UMC 0.11um LL Logic/FSG process true 3.3V Generic IO.
General Purpose IO IP, 5V tolerance, UMC 0.11um LL/FSG process
UMC 0.11um LL Logic/FSG process 5V tolerant Generic IO.
General Purpose IO IP, UMC 0.11um HS/FSG process
UMC 0.11um HS process true 3.3V standard IO.
General Purpose IO IP, 5V tolerance, UMC 0.11um HS/FSG process
UMC 0.11um HS process 5V tolerant standard IO.
General Purpose IO IP, UMC 0.11um SP/FSG process
UMC 0.11um SP/FSG Logic process true 3.3V Generic IO.
General Purpose IO IP, 5V tolerance, UMC 0.11um SP/FSG process
UMC 0.11um SP/FSG Logic process 5V tolerant Generic IO.
General Purpose IO IP, BOAC (Bonding Over Active Circuit), 5V tolerance, UMC 55nm SP process
UMC 55nm SP/RVT Logic process 5VT Generic IO for BOAC.
Specialty Analog ESD IO IP, 3.3V, UMC 40nm LP process
UMC 40nm LP/RVT Logic process, 3.3V Analog ESD IO Cell Library (using 2.5V overdrive 3.3V MOS).
Specialty Analog ESD IO IP, 1.8V Operations, UMC 28nm HPM process
UMC 28nm Logic and Mixed-Mode HPM process, 1.8V Analog ESD IO Cell Library.
Specialty Analog ESD IO IP, 1.1V Operations, UMC 40nm LP process
UMC 40nm LP/RVT Logic process, 1.1V Analog ESD IO Cell Library.
Specialty Analog ESD IO IP, 0.9V Operations, UMC 28nm HPM process
UMC 28nm Logic and Mixed-Mode HPM process, 0.9V Analog ESD IO Cell Library.
Specialty Analog ESD IO IP, UMC 0.18um LL process
UMC 0.18um LL Logic process 3.3V Analog ESD IO set Cell Library.
Specialty Analog ESD IO IP, UMC 0.18um LL process
UMC 0.18um LL Logic process 1.8V Analog ESD IO set Cell Library.
ROM Compiler IP, UMC 90nm CIS process
UMC 90nm CMOS Image Sensor process 1P3M Via ROM compiler.
ROM Compiler IP, UMC 55nm LP process
UMC 55nm LP Logic process Via1 ROM memory compiler.
ROM Compiler IP, UMC 55nm eHV process
UMC 55nm eHV PeriHVT Via1 ROM compiler.
ROM Compiler IP, UMC 55nm eFlash process
UMC 55nm eFlash process with peripheral HVT Pcode ROM compiler.
ROM Compiler IP, UMC 40nm LP process
UMC 40 LP/RVT Low-K Logic process Via1 ROM memory compiler.