Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track Cell Library with LMINUS (C30 LVT).
- UMC
- 28nm
- HLP
Standard cell libraries are fundamental building blocks for ASIC and SoC design, providing a set of pre-characterized logic cells used in digital circuit implementation.
These libraries include essential components such as logic gates, flip-flops, latches, and buffers, enabling efficient synthesis and physical design flows.
This catalog allows you to compare standard cell libraries from leading vendors based on performance, power consumption, area, and process node compatibility.
Whether you are targeting high-performance computing, low-power mobile designs, or cost-sensitive applications, you can find the right standard cell library for your project.
Standard Cell (MiniLib) Library IP, LVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track Cell Library with LMINUS (C30 LVT).
Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library with LPLUS (C38).
Standard Cell (MiniLib) Library IP, HVT, 7 tracks, UMC 28nm HLP process
UMC 28nm HLP/HVT Logic and Mixed-Mode process 7-Track Generic Core Cell Library.
Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.11um eFlash/HS process
UMC 0.11um eFlash/EE2PROM AL process Mini-Library+ (6-Track) Library.
Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.18um LL process
UMC 0.18um MM/RF process Mini Cell Library.
Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.18um LL process
UMC 0.18um MM/RF process Mini Cell Library.
Standard Cell (MiniLib) Library IP, 7 tracks, UMC 0.18um G2 process
UMC 0.18um GII Logic process high-density/Low Power Core Cell Library.
Standard Cell (MiniLib) Library IP, 6 tracks, UMC 0.13um LL/FSG process
UMC 0.13um LL/FSG Logic process Mini-Library+.
Standard Cell (High Voltage) Library IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG process 3.3V Device Core Cell Library for RTC/PMU usage.
Standard Cell (High Voltage) Library IP, 9 tracks, UMC 0.13um eHV process
UMC 0.13um Embedded High Voltage 1.5V Core Cell Library.
Standard Cell (Generic) Library IP, RVT, 8 tracks, UMC 55nm LP process
UMC 55nm LP/RVT Low-K Logic process 8-Track Generic Core Cell Library.
Standard Cell (Generic) Library IP, LVT, 8 tracks, UMC 55nm LP process
UMC 55nm LP/LVT Low-K Logic process 8-Track Generic Core Cell Library.
Standard Cell (Generic) Library IP, HVT, 8 tracks, UMC 55nm LP process
UMC 55nm LP/HVT Low-K Logic process 8-Track Generic Core Cell Library.
Standard Cell (Generic) Library IP, RVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Logic process 12-Track high speed Generic Core Cell Library (C50).
Standard Cell (Generic) Library IP, RVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Logic process 12-Track high speed Generic Core Cell Library (C40).
Standard Cell (Generic) Library IP, LVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Logic process 12-Track high speed Generic Core Cell Library (C50).
Standard Cell (Generic) Library IP, LVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/LVT Logic process 12-Track high speed Standard Core Cell Library.
Standard Cell (Generic) Library IP, HVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/HVT Logic process 12-Track high speed Generic Core Cell Library (C50).
Standard Cell (Generic) Library IP, HVT, 12 tracks, UMC 40nm LP process
UMC 40nm LP/HVT Logic process 12-Track high speed Generic Core Cell Library (C40).
Standard Cell (Generic) Library IP, RVT, 9 tracks, UMC 40nm LP process
UMC 40nm LP/RVT Logic process 9-Track Standard Cell Library (C50 Generic Core).