UMC 40nm uLP/LVT Logic Process SYNS-like 7T GENERIC CORE Cell Library
UMC 40nm uLP/LVT Logic Process SYNS-like 7T GENERIC CORE Cell Library
- UMC
- 40nm
- ULP
Standard cell libraries are fundamental building blocks for ASIC and SoC design, providing a set of pre-characterized logic cells used in digital circuit implementation.
These libraries include essential components such as logic gates, flip-flops, latches, and buffers, enabling efficient synthesis and physical design flows.
This catalog allows you to compare standard cell libraries from leading vendors based on performance, power consumption, area, and process node compatibility.
Whether you are targeting high-performance computing, low-power mobile designs, or cost-sensitive applications, you can find the right standard cell library for your project.
UMC 40nm uLP/LVT Logic Process SYNS-like 7T GENERIC CORE Cell Library
UMC 40nm uLP/LVT Logic Process SYNS-like 7T GENERIC CORE Cell Library
UMC 40nm uLP/HVT Logic Process SYNS-like 7T GENERIC CORE Cell Library
UMC 40nm uLP/HVT Logic Process SYNS-like 7T GENERIC CORE Cell Library
UMC 28nm HPM/LVT Logic Process 12-track generic_core library with LPKUS (C38)
UMC 28nm HPM/LVT Logic Process 12-track generic_core library with LPKUS (C38)
UMC 28nm HPM/LVT Logic Process 12-track generic cell library with LMINUS (C-31)
UMC 28nm HPM/LVT Logic Process 12-track generic cell library with LMINUS (C-31)
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track generic_core cell library (C35)
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 12-track generic_core cell library (C35)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track Standard Generic core cell library (C30)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 12-track Standard Generic core cell library (C30)
UMC 0.18um GII Logic Process 3.3V core cell library
UMC 0.18um GII Logic Process 3.3V core cell library
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track ECO_M1 cell library enhanced for routing (C35)
UMC 28nm HPC/RVT Logic and Mixed-Mode Process 9-track ECO_M1 cell library enhanced for routing (C35)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track ECO_M1 cell library enhanced for routing (C35)
UMC 28nm HPC/LVT Logic and Mixed-Mode Process 9-track ECO_M1 cell library enhanced for routing (C35)
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 9-track ECO_M1 cell library enhanced for routing (C35)
UMC 28nm HPC/HVT Logic and Mixed-Mode Process 9-track ECO_M1 cell library enhanced for routing (C35)
UMC 40nm LP/RVT Logic Process SYNS-like 9T ECO_M1 Cell Library
UMC 40nm LP/RVT Logic Process SYNS-like 9T ECO_M1 Cell Library
UMC 40nm LP/LVT Logic Process SYNS-like 9T ECO_M1 Cell Library
UMC 40nm LP/LVT Logic Process SYNS-like 9T ECO_M1 Cell Library
UMC 40nm LP/HVT Logic Process SYNS-like 9T ECO_M1 Cell Library
UMC 40nm LP/HVT Logic Process SYNS-like 9T ECO_M1 Cell Library
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track eco_m1 cell library
UMC 28nm HPM/RVT Logic and Mixed-Mode Process 7-track eco_m1 cell library
UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library
UMC 28nm HPM/LVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library
UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library
UMC 28nm HPM/HVT Logic and Mixed-Mode Process 7-track ECO_M1 cell library
UMC 90nm SP/RVT LowK Logic Process ECO M1 core cell library
UMC 90nm SP/RVT LowK Logic Process ECO M1 core cell library
UMC 0.13um HS/FSG Logic Process metal2-start programming gate array cell library for FSC0H_J (ECO_M2)
UMC 0.13um SP/FSG Logic Process Metal1 Start ECO core cell library
UMC 0.13um SP/FSG Logic Process Metal1 Start ECO core cell library
UMC 0.13um LL/FSG Logic Process miniLib+ M1 ECO cells
UMC 0.13um LL/FSG Logic Process miniLib+ M1 ECO cells