TSMC CL013G 130nm Clock Generator PLL - 68MHz-340MHz
True Circuits, Inc.
•
HQ:
USA
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
- TSMC
- 130nm
- G
Compare 3,961 TSMC IP Cores from 81 vendors
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TSMC CL013LV 130nm Clock Generator PLL - 320MHz-1600MHz
True Circuits, Inc.• HQ: USAThe Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
- TSMC
- 130nm
- LV
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TSMC CL013LV 130nm Clock Generator PLL - 80MHz-400MHz
True Circuits, Inc.• HQ: USAThe Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
- TSMC
- 130nm
- LV
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TSMC CL013LV 130nm Deskew PLL - 80MHz-400MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 130nm
- LV
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TSMC CL013LV 130nm Deskew PLL - 160MHz-800MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 130nm
- LV
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TSMC CL013G 130nm Deskew PLL - 68MHz-340MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 130nm
- G
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TSMC CL013G 130nm Deskew PLL - 136MHz-680MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 130nm
- G
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TSMC CL015LV 150nm Deskew PLL - 70MHz-350MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 150nm
- LV
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TSMC CL015LV 150nm Deskew PLL - 140MHz-700MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 150nm
- LV
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TSMC CL015G 150nm Deskew PLL - 65MHz-325MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 150nm
- G
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TSMC CL015G 150nm Deskew PLL - 130MHz-650MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 150nm
- G
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TSMC CL018E 180nm Deskew PLL - 65MHz-325MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 180nm
- E
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TSMC CL018E 180nm Deskew PLL - 130MHz-650MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 180nm
- E
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TSMC CL018G 180nm Deskew PLL - 110MHz-550MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 180nm
- G
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TSMC CL018G 180nm Deskew PLL - 55MHz-275MHz
True Circuits, Inc.• HQ: USAThe Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
- TSMC
- 180nm
- G
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TSMC CL013LV 130nm Clock Generator PLL - 160MHz-800MHz
True Circuits, Inc.• HQ: USAThe Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
- TSMC
- 130nm
- LV
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Dolphin Semiconductor• HQ: France
Foundry sponsored - sROMet compiler - TSMC 55 nm uLPeFlash - Non volatile memory optimized for high density and low power - Dual …
- TSMC
- 40nm
- ULP eFlash
- Pre-Silicon
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TSMC N6 1.8V/3.3V Fail-Safe Fail-Tolerant SMBus
Synopsys, Inc.• HQ: USASynopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliabilit…
- TSMC
- 6nm
- N6
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Synopsys, Inc.• HQ: USA
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliabilit…
- TSMC
- 7nm
- N7A
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TSMC N7 1.2V/1.8V/2.5V/3.3v General Purpose IO with CDM 7A, AG2 Platform
Synopsys, Inc.• HQ: USASynopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliabilit…
- TSMC
- 7nm
- N7A