TSMC IP Cores

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.

• TSMC
• 12nm
• FFC

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.

• TSMC
• 12nm
• FFC

HCLTech offers IP POR hcl_por_t40_v1 circuit provides a reset signal to the chip when supply ramps up so that the chip always sta…

• TSMC
• 40nm
• G

HCLTech Offers IP Process Monitor IP (hcl_procmon_t40_v2) consists of three ring oscillators namely RVT Ring Oscillator, Thick ox…

• TSMC
• 40nm
• G

The low voltage Standard Cell Library for the TSMC N3P process represents a breakthrough in power efficiency for high performance…

• TSMC
• 3nm
• N3P
• Pre-Silicon

The Synopsys Foundation IP optimized for the TSMC’s 22nm Ultra Low Leakage (ULL) process provides designers an extensive offering…

• TSMC
• 22nm
• ULL
• Available on request

The AT256X16T152LP0AA is organized as 256 bits by 16 one-time programmable in 16-bit read and 1-bit program modes.

• TSMC
• 152nm
• G
• Silicon Proven

The ATO00128X8TS055ULP3NA is organized as 128x8 one-time programmable (OTP) in 8-bit read and 1-bit program modes.

• TSMC
• 55nm
• GP
• Silicon Proven

The ATO0001X32TS180SGE3NA is organized as 1 by 32 bits one-time programmable (OTP).

• TSMC
• 180nm
• BCDG2
• Silicon Proven

The ATO0768X39TS055ULP4NA is organized as 768x39 one-time programmable (OTP).

• TSMC
• 55nm
• ULP
• Silicon Proven

The ATO016KX33TS040LLP7ZA is organized as 16K-bits by 33 one-time programmable (OTP).

• TSMC
• 40nm
• LP
• Silicon Proven

The ATO00512X8TS012FFC8EA is organized as 512 bits by 8 one-time programmable (OTP).

• TSMC
• 12nm
• FFC
• Silicon Proven

eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…

• TSMC
• 180nm
• BCDG2
• In Production

eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…

• TSMC
• 130nm
• BCD/BCD+
• In Production

eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…

• TSMC
• 90nm
• CIS
• In Production

eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…

• TSMC
• 180nm
• BCDG2
• In Production

eMemory's NeoBit OTP (One-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed-m…

• TSMC
• 110nm
• In Production

NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementatio…

• TSMC
• 90nm
• CIS
• In Production

NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementatio…

• TSMC
• 180nm
• BCDG2
• In Production

NeoFuse is a small-form factor logic NVM technology with the advantages of working on low power and being reliable and secure.

• TSMC
• 12nm
• FFC
• In Production