The 12-bit 500 MSPS IQ DAC employs a high-performance current steering architecture and provides optional differential current ou…
- 12 Bit
- TSMC
- 65nm
- GP
- Pre-Silicon
The 12-bit 500 MSPS IQ DAC employs a high-performance current steering architecture and provides optional differential current ou…
12-bit 1-channel 44/70/90 MSPS pipeline ADC
180TSMC_ADC_13 is a low-power high-speed 12 bit ADC that employs high-performance differential pipeline architecture.
2 Gbps Rail to Rail LVDS receiver
065TSMC_LVDS_10 is LVDS receiver with rail to rail input range.
Ideal for use as watch-dog timers and core clock generators for MCUs and low-power chips with competitive features.
Combined GNSS/TV/FM multi-frequency receiver
NT2024 is a 4-channel RF front end designed to perform a simultaneous reception, conversion, filtering and amplifying of GPS/Gali…
065TSMC_OSC_02 is a CMOS inverter of a pierce-type variation with an integrated Crystal (Xtal) oscillator that is optimized in pa…
50 - 800 MHz phase-locked loop
The synthesizer forms clock signal with frequency from 50 to 800 MHz.
Process/Voltage/Temperature Sensor (Supply voltage 2.5V/1.1V)
PVT Detector is a unique solution intended to continuously monitor IC status at several on-die locations.
1 – 600 MHz frequency synthesizer
The synthesizer produces stable clock signal in range from 1 to 600MHz.
1.2 Gbps LVDS transmitter/receiver
The interface to the core logic in receiver mode includes the signal pins (out_p and out_n) to receive data and the control pins …
12-bit 2-channel up to 50 MSPS current steering DAC
180TSMC_DAC_07 is a 12-bit 50 MSPS dual current steering DAC contains two DAC cores, reference current, bandgap, configuration re…
12-bit 1-channel 20 to 100 MSPS ADC
The low-power high-speed 12-bit ADC employs a high-performance differential pipeline architecture.
12-bit 1-channel 4 MSPS SAR ADC
065TSMC_ADC_10 employs high-performance differential successive approximation architecture with sub-ranging and output offset com…
12-bit 4-channel 20 to 100 MSPS ADC
Quad-channel 12-bit 20 – 100 MSPS ADC contains four ADC channels, LVDS receiver, reference voltages and reference currents circui…
This device is designed to generate a quadrature heterodyne (oscillator) signal.
1 Gbps Rail to Rail LVDS receiver
065TSMC_LVDS_08 is LVDS receiver with rail to rail input range.
065TSMC_LVDS_07 is LVDS transmitter.
16-bit 2-channel 25 kHz bandwidth delta-sigma stereo, audio DAC
Delta-sigma stereo, audio DAC contains: reference voltage, control logic, digital buffers I2S interface (ws, sd, sck, gpio), two …
The 10-bit 100 MSPS ADC employs a high-performance front-end sample-and-hold with differential multi-stage pipelined architecture…
Library of LVDS IOs cells for TSMC 65LP
The nSIO2000_TS65LP_2V5_1V2 library is an IO cells library combining various LVDS and general purpose I/O powered at 2.5V/1.2V or…