TSMC CLN28HPM 28nm Deskew PLL - 700MHz-3500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CLN20SOC 20nm Deskew PLL - 175MHz-875MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CLN20SOC 20nm Deskew PLL - 350MHz-1750MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CLN20SOC 20nm Deskew PLL - 700MHz-3500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference.
TSMC CLN28HPL 28nm Clock Generator PLL - 110MHz-550MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN28HPL 28nm Clock Generator PLL - 220MHz-1100MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN28HPL 28nm Clock Generator PLL - 440MHz-2200MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN28HPM 28nm Clock Generator PLL - 175MHz-875MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN28HPM 28nm Clock Generator PLL - 350MHz-1750MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN28HPM 28nm Clock Generator PLL - 700MHz-3500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN20SOC 20nm Clock Generator PLL - 175MHz-875MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN20SOC 20nm Clock Generator PLL - 350MHz-1750MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
TSMC CLN20SOC 20nm Clock Generator PLL - 700MHz-3500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096.
LVDS-based IOs The Bi-directional LVDS is in production from 90nm CMOS to 16/12nm FinFET and taped out in 7nm FinFET.
Configurable Turbo Product Codec
In channel coding redundancy is inserted in the transmitted information bit-stream.
Temperature sensor consists of built-in 10-bit R-2R DAC, diode and own reference voltage former.
Embedded MTP (Multi-Time Programmable) IP,4x8 bits for 2.5V/5V Logic
eMemory's NeoBit MTP (Multi-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed…
Embedded MTP (Multi-Time Programmable) IP,1x32 bits for 1.8V/5V/32V HV
eMemory's NeoBit MTP (Multi-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed…
Embedded MTP (Multi-Time Programmable) IP,4x8 bits for 2.5V/5V/40V BCD
eMemory's NeoBit MTP (Multi-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed…
Embedded MTP (Multi-Time Programmable) IP,4x8 bits for 2.5V/3.3V/20V HV
eMemory's NeoBit MTP (Multi-Time Programmable) IP can be implemented seamlessly in various CMOS technologies such as logic, mixed…