Switching regulator, inductor-based, in dual mode (PFM and PWM) & high efficiency
eSR-Niagara-Bu-dm-ref-[1.62-3.63]-[0.8-2.5].01, as any Power Management Virtual Component designed by Dolphin Design, is readily …
- TSMC
- 55nm
- GP
- Pre-Silicon
Power management IP cores are essential components in modern SoC and ASIC designs, enabling efficient power regulation, distribution, and energy optimization.
These IP cores include functions such as voltage regulators, DC-DC converters, LDOs, battery management, and power monitoring, ensuring reliable and energy-efficient system operation.
This catalog allows you to compare power management IP cores from leading vendors based on efficiency, power consumption, integration level, and process node compatibility.
Whether you are designing mobile devices, automotive systems, IoT products, or high-performance computing platforms, you can find the right power management IP for your system.
Switching regulator, inductor-based, in dual mode (PFM and PWM) & high efficiency
eSR-Niagara-Bu-dm-ref-[1.62-3.63]-[0.8-2.5].01, as any Power Management Virtual Component designed by Dolphin Design, is readily …
TON timer, provides COT switching time based on Vin and Vout
TON timer, provides COT switching time based on Vin and Vout
4.25V...15V to 3.3V/120mA LDO
DCDC regu power stage, includes bootstrap regulator
DCDC regu power stage, includes bootstrap regulator
LS current replica block, 1:100'000
LS current replica block, 1:100'000, for LS switch current measurement
HS current replica block, 1:100'000
HS current replica block, 1:100'000, for HS switch current measurement
Ripple injector, feedback block for regulator output ripple measurement
LS power switch driver
HS power switch driver
HS bootstrap driver for HS NMOS gate voltage generation
HS bootstrap driver for HS NMOS gate voltage generation
Zero-cross detector and valley OCP block, trimmable
Zero-cross detector and valley OCP block, trimmable
HS current protection circuit
Charge pump, makes Vin-3.3V voltage
Charge pump, makes Vin-3.3V voltage
Bandgap cell, 1.2V, trimmable, no buffering
Bandgap cell, 1.2V, trimmable, no buffering
Bandgap (1.2V)+ buffers + current bias
Bandgap (1.2V)+ buffers (2.56V, 1.2V) + current bias (n*0.5uA), all trimmable
Voltage Regulator LDO, Adjustable 1.1V Output
The ShortLink voltage regulator 'SL40LP_1V1LDO_1' is an analogue Low Drop-Out regulator based on a two-stage architecture.
Bandgap Reference 1.22V bandgap, 1V & 0.5V Output
The ShortLink voltage reference and bias generator 'SL40LP_1V2BG_1' is based on a bandgap architecture.
Output driver stage for DCDC - TSMC 180nm
Output driver stage for DCDC - TSMC 180nm
Digital controller for DCDC, asynchronous & synchronous parts - TSMC 180nm
Digital controller for DCDC, asynchronous & synchronous parts - TSMC 180nm
PMOS 1.5A Over Current Protection - TSMC 180nm
PMOS 1.5A Over Current Protection - TSMC 180nm