Power-On Reset - Threshold (1.6V1.8V), Low Current (1.5µA) - Silterra 0.18 um
This macro-cell is a low consumption Power-On Reset (POR) core designed for SilTerra 0.18μm CL180GH5 5V CMOS technology.
- Silterra
- 180nm
- G
- Silicon Proven
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
Power-On Reset - Threshold (1.6V1.8V), Low Current (1.5µA) - Silterra 0.18 um
This macro-cell is a low consumption Power-On Reset (POR) core designed for SilTerra 0.18μm CL180GH5 5V CMOS technology.
Ultra Low Power PMU - (2.18µW) - SilTerra 0.18 um
This macro-cell is an ultra low consumption Power Management Unit (PMU) core designed for Silterra 0.18µm C18G CMOS technology TO…
2MHz Ultra Low Power Oscillator - Ultra low power (720nW) Silterra 0.18 um
This macro-cell is a general purpose, ultra low power internal oscillator core designed for SilTerra 0.18μm CL180G CMOS technolog…
Li-Ion Battery Charger - ±1% Accuracy (4.2V) / Up to 1500mA Fast Charge - Silterra 0.18 um
This macro-cell is a precision linear Li-Ion battery charger core (4.2V, +/-1%) designed for SilTerra CL180GH5 0.18μm CMOS techno…
Power-On Reset - Flexible Threshold (1-1.3V), Ultra Low Current (100nA) - Silterra 0.18 um
This macro-cell is an ultra low consumption Power-On Reset (POR) core designed for SilTerra 0.18μm CL180G CMOS technology.
Silterra 0.18um ULL Process 7track Power Management Kit
Silterra 0.18um Ultra Low Leakage 7track PMK Library
This IP is a programmable Analog PLL suitable for high speed clock generation.