Power-On Reset - Flexible Threshold (1-1.3V), Ultra Low Current (100nA) - Silterra 0.18 um
This macro-cell is an ultra low consumption Power-On Reset (POR) core designed for SilTerra 0.18μm CL180G CMOS technology.
Overview
This macro-cell is an ultra low consumption Power-On Reset (POR) core designed for SilTerra 0.18μm CL180G CMOS technology.
The threshold sensing voltage can be configured from 1V to 1.3V (default is 1.15V). A hysteresis of 120mV is added to avoid false reset glitches in noisy supplies. This value can be digitally configured from 70mV to 200mV. The POR features an internal process compensated voltage reference. It requires an external 7.75nA current bias (sink), which can be implemented using CM1014ff IP.
The core is easily retargeted to any other CMOS technology.
Key features
- Supply voltage: 1.0–2.0V
- Configurable assertion threshold (1.0V– 1.3V)
- Adjustable hysteresis (70mV– 200mV)
- Ultra low current consumption (100nA)
- Indicative area: 0.0064mm2
Block Diagram
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| Silterra | 180nm | G | Silicon Proven |
Specifications
Identity
Files
Note: some files may require an NDA depending on provider policy.
Provider
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Frequently asked questions about Power-On Reset (POR) IP cores
What is Power-On Reset - Flexible Threshold (1-1.3V), Ultra Low Current (100nA) - Silterra 0.18 um?
Power-On Reset - Flexible Threshold (1-1.3V), Ultra Low Current (100nA) - Silterra 0.18 um is a Power On Reset (POR) IP core from Chipus Microelectronics listed on Semi IP Hub. It is listed with support for silterra Silicon Proven.
How should engineers evaluate this Power On Reset (POR)?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Power On Reset (POR) IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.