Vendor: Chipus Microelectronics Category: Power On Reset (POR)

Power-On Reset - Flexible Threshold (1­-1.3V), Ultra Low Current (100nA) - Silterra 0.18 um

This macro-cell is an ultra low consumption Power-On Reset (POR) core designed for SilTerra 0.18μm CL180G CMOS technology.

Contact Provider Request Datasheet
Silterra 180nm G Silicon Proven View all specifications

Overview

This macro-cell is an ultra low consumption Power-On Reset (POR) core designed for SilTerra 0.18μm CL180G CMOS technology.

The threshold sensing voltage can be configured from 1V to 1.3V (default is 1.15V). A hysteresis of 120mV is added to avoid false reset glitches in noisy supplies. This value can be digitally configured from 70mV to 200mV. The POR features an internal process compensated voltage reference. It requires an external 7.75nA current bias (sink), which can be implemented using CM1014ff IP.

The core is easily retargeted to any other CMOS technology.

Key features

  • Supply voltage: 1.0–2.0V
  • Configurable assertion threshold (1.0V– 1.3V)
  • Adjustable hysteresis (70mV– 200mV)
  • Ultra low current consumption (100nA)
  • Indicative area: 0.0064mm2

Block Diagram

CM1413ff block diagram

Silicon Options

Foundry Node Process Maturity
Silterra 180nm G Silicon Proven

Specifications

Identity

Part Number
CM1413ff
Vendor
Chipus Microelectronics
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Chipus Microelectronics

Learn more about Power On Reset (POR) IP core

Method for Booting ARM Based Multi-Core SoCs

In the boot process various modules/peripherals (like clock controller or security handing module and other master/slaves) initialized as per the SoC architecture and customer applications. In Multi core SoCs, first primary core (also called booting core) start up in boot process and then secondary cores are enabled by software.

Analysis of RDC Paths for a million gate SoC

Reset is necessary to initialize the system and reach to a known state. Just like multiple clocks are required in an SoC to sustain various use models and performance, multiple resets are designed to cater different functional requirements. With this advent we also invite some issues due to crossings among different reset domains. In a sequential design, if the reset of source register is different from the reset of destination register even though the data path is in same clock domain, this will become asynchronous crossing path and can cause metastability at destination register.

The silicon enigma: Bridging the gap between simulation and silicon

VLSI design teams are eagerly anticipating the full functional fab out Silicon to portray their months of hard work, on the other hand the Test teams are busy planning their functional coverage (to fill in the gaps of scan (atpg) patterns coverage holes) but more often than not, the unexpected happens and the teams are busy debugging the Si bring up for functional cases. This paper is trying to highlight the seemingly innocuous issues that occur on first few day of Si bring up and proactive steps that would help reduce these cycle.

BIST Verification at SoC level

With the increase complexity of modern day SoCs, the number of memory blocks and LBIST partitions are increasing, which is in turn making the verification efforts quite challenging. This paper highlights the key points to keep in mind while deciding the verification strategy for self-test, and what are the road-blocks in executing this “ideal” verification plan.

High Density - Low power Flip-Flop

In a current trend of SoC Design, IC’s are becoming more and more complex so the challenges of meeting all the design requirements have become increasingly difficult.

Frequently asked questions about Power-On Reset (POR) IP cores

What is Power-On Reset - Flexible Threshold (1­-1.3V), Ultra Low Current (100nA) - Silterra 0.18 um?

Power-On Reset - Flexible Threshold (1­-1.3V), Ultra Low Current (100nA) - Silterra 0.18 um is a Power On Reset (POR) IP core from Chipus Microelectronics listed on Semi IP Hub. It is listed with support for silterra Silicon Proven.

How should engineers evaluate this Power On Reset (POR)?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Power On Reset (POR) IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP