Foundation Library IP cores provide the fundamental building blocks required for ASIC and SoC implementation, enabling efficient digital design, physical synthesis, timing closure, and manufacturing across advanced semiconductor process nodes.
This category includes both Standard Cell Libraries and I/O Pad Libraries, covering logic cells, sequential elements, low-power cells, level shifters, ESD-protected I/O interfaces, and process-specific implementation libraries optimized for leading foundries.
This catalog enables semiconductor engineers to evaluate and compare Foundation Library IP solutions from multiple vendors based on process node support, PPA (Power, Performance, Area) characteristics, library characterization quality, voltage domains, reliability requirements, and integration with modern EDA design flows.
Whether targeting AI accelerators, automotive SoCs, networking devices, wireless chipsets, or high-performance computing applications, engineers can identify the Foundation Library IP best suited to their technology, performance, and manufacturing requirements.
TSMC 12nm 0V8 ESD Local Protection Low Cap
This TSMC 12nm 0.8V ESD Local Protection IP provides low-capacitance, low-leakage protection for sensitive I/O and interface pins.
SMIC 28nm 0V75 ESD Power Clamp
This specific IP macro is designed in 28nm and can be ported to other technologies upon request using Sofics in-house design tool flow.
SMIC 28nm 0V75 ESD Local Clamp – Low Capacitance
This specific IP macro is designed in 28nm and can be ported to other technologies upon request using Sofics in-house design tool flow.
This TSMC 3nm 3.3V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs.
This TSMC 3nm 1.8V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs. The IP macro is designed in TSMC 3nm.
This TSMC 2nm 1.8V GPIO IP provides configurable, overvoltage-tolerant I/O functionality for advanced-node designs. The IP macro is designed in TSMC 2nm.
This specific IP macro is designed in TSMC 22nm and can be ported to other technologies upon request using Sofics in-house design tool flow.