Vendor: SmartDV Category: SRAM

FCRAM Synthesizable Transactor

FCRAM Synthesizable Transactor provides a smart way to verify the FCRAM component of a SOC or a ASIC in Emulator or FPGA platform.

Overview

FCRAM Synthesizable Transactor provides a smart way to verify the FCRAM component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's FCRAM Synthesizable Transactor is fully compliant with standard FCRAM Specification and provides the following features.

Key features

  • Supports 100% of FCRAM protocol standard FCRAM specifications
  • Supports all the FCRAM commands as per the specs
  • Supports up to 512MB device density
  • Supports up to four internal banks
  • Supports programmable write latency
  • Supports programmable burst lengths:
    • 2
    • 4
    • 8
    • 16
  • Supports sequential burst type
  • Supports burst order
  • Supports all mode registers programming
  • Checks for following:
    • Check-points include power on, initialization and power off rules
    • State based rules, active command rules
    • Read/Write command rules etc
    • All timing violations
  • Supports self refresh, power down and deep power down operation
  • Supports auto refresh operation
  • Supports additional RDQS toggle (ART)
  • Supports write data mask and data strobe features
  • Supports background refresh and burst terminate operations
  • Supports clock stop capability during idle periods
  • Supports both synchronous and asynchronous on-die termination modes
  • Supports all types of timing and protocol violation detection
  • Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations

Block Diagram

FCRAM Transactor block diagram

Benefits

  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms

What’s Included?

  • Synthesizable transactors
  • Complete regression suite containing all the FCRAM testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all DPI, class, task and function's used in verification env
  • Documentation contains User's Guide and Release notes

Specifications

Identity

Part Number
FCRAM Transactor
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

Learn more about SRAM IP core

A Process-Aware Hybrid Si/IGO Monolithic-3D 6T SRAM with BEOL Pass-Gates for the 2nm Node

The authors propose a monolithic-3D (M3D) 6T SRAM at the 2nm node, integrating BEOL IGO pass-gates (PGs) with an all-silicon nanosheet latch, buried power rails (BPRs), and Ru interconnects. TCAD calibrated to a state-of-the-art double-gate IGO transistor with a tri-layer HfO2/ZrO2/HfO2 (HZH) gate stack is combined with virtual fabrication and 3D parasitic extraction to realize the first process-aware layout of this topology.

Frequently asked questions about SRAM IP cores

What is FCRAM Synthesizable Transactor?

FCRAM Synthesizable Transactor is a SRAM IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this SRAM?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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