ROM Compiler IP, UMC 0.11um SP process
UMC 0.11um high speed Logic process synchronous Via-1 ROM memory compiler.
- UMC
- 110nm
- SP
Embedded memory IP cores are fundamental components in modern SoC and ASIC designs, providing fast and efficient on-chip data storage for processors, accelerators, and peripherals.
These IP cores encompass a broad range of volatile and non-volatile memory technologies, including SRAM for high-speed data storage, ROM for fixed program and boot code storage, register files for processor and accelerator architectures, as well as EEPROM, eFuse/OTP, and MTP (Multiple-Time Programmable) memories for configuration data, security credentials, device calibration, and permanent system information.
This catalog allows you to compare embedded memory IP cores from leading vendors based on density, access time, power consumption, and process node compatibility.
Whether you are designing high-performance processors, AI accelerators, automotive systems, or IoT devices, you can find the right embedded memory IP for your design.
ROM Compiler IP, UMC 0.11um SP process
UMC 0.11um high speed Logic process synchronous Via-1 ROM memory compiler.
ROM Compiler IP, UMC 0.11um LL process
UMC 0.11um LL process synchronous Via-1 ROM memory compiler.
ROM Compiler IP, UMC 0.11um HS/AE process
UMC 0.11um HS/AE (AL Enhancement) Logic process synchronous via-1 ROM memory compiler.
ROM Compiler IP, UMC 0.11um eFlash/HS process
UMC 0.110um eFlash HS process Via1 ROM compiler.
One Port Register File Compiler IP, UMC 90nm SP process
UMC 90nm SP/RVT low_K Logic process synchronous One Port Register File.
One Port Register File Compiler IP, UMC 90nm SP process
UMC 90nm Logic standard performance process synchronous high density Single Port Register File SRAM memory compiler.
One Port Register File Compiler IP, UMC 55nm eFlash process
UMC 55nm eFlash One Port Register File with Power Gating.
One Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP One Port Register File with Sleep/Retention/Nap mode & peripheral LVT feature.
One Port Register File Compiler IP, UMC 40nm LP process
UMC 40nm LP One Port Register File with Sleep/retention/Nap mode feature.
One Port Register File Compiler IP, UMC 28nm SP process
UMC 28nm Logic process synchronous Ultra high speed Single Port Register File SRAM memory compiler.
One Port Register File Compiler IP, UMC 28nm HLP process
UMC 28nm HLP Logic process One Port Register File with LVT.
One Port Register File Compiler IP, UMC 28nm HLP process
UMC 28nm HLP/ Low-K One Port Register File.
One Port Register File Compiler IP, UMC 28nm HLP process
UMC 28nm HLP/UHS One Port Register File compiler with peripheral LVT.
One Port Register File Compiler IP, UMC 0.25um process
UMC 0.25um Logic process synchronous Single Port Register File SRAM memory compiler.
One Port Register File Compiler IP, UMC 0.18um LL process
UMC 0.18um LL Logic process synchronous Single Port Register File SRAM memory compiler.
One Port Register File Compiler IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process synchronous Single Port Register File SRAM memory compiler.
One Port Register File Compiler IP, UMC 0.13um SP process
UMC 0.13-micron 1.2V high speed (HS) Logic process synchronous Low Power Single Port Register File SRAM compiler.
One Port Register File Compiler IP, UMC 0.13um LL process
UMC 0.13um LL Logic/FSG process high density synchronous Single Port Register File SRAM memory compiler.
One Port Register File Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/FSG Logic process synchronous Single Port Register File SRAM memory compiler.
One Port Register File Compiler IP, UMC 0.13um HS/FSG process
UMC 0.13um HS/LL fusion (FSG) process high density synchronous Single Port Register File SRAM memory compiler.