UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm ULP/LowK process Single-Port SRAM
- UMC
- 55nm
- ULP
- Pre-Silicon
Embedded memory IP cores are fundamental components in modern SoC and ASIC designs, providing fast and efficient on-chip data storage for processors, accelerators, and peripherals.
These IP cores encompass a broad range of volatile and non-volatile memory technologies, including SRAM for high-speed data storage, ROM for fixed program and boot code storage, register files for processor and accelerator architectures, as well as EEPROM, eFuse/OTP, and MTP (Multiple-Time Programmable) memories for configuration data, security credentials, device calibration, and permanent system information.
This catalog allows you to compare embedded memory IP cores from leading vendors based on density, access time, power consumption, and process node compatibility.
Whether you are designing high-performance processors, AI accelerators, automotive systems, or IoT devices, you can find the right embedded memory IP for your design.
UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm ULP/LowK process Single-Port SRAM
UMC 55nm eFlash process synchronous low power feature RVT peripheral high density single port SRAM compiler with row redundancy.
UMC 55nm eFlash process process synchronous low power feature RVT peripheral high density single port SRAM compiler.
UMC 55nm eHV process ; Single-Port SRAM compiler with Row redundancy
UMC 55nm eHV process ; Single-Port SRAM compiler with Row redundancy
UMC 55nm eHV process;Single-Port SRAM compiler
UMC 55nm eHV process;Single-Port SRAM compiler
ULL Sigle Port SRAM with HVT Row redundancy, UMC 40nm LP process.
ULL Sigle Port SRAM with HVT Row redundancy, UMC 40nm LP process.
ULL Single Port SRAM with peri HVT, UMC 40nm LP process.
ULL Single Port SRAM with peri HVT, UMC 40nm LP process.
UMC 40nm Low Power Process Single-Port SRAM for dual power rail
UMC 40nm Low Power Process Single-Port SRAM for dual power rail
UMC 40nm LP Logic Process Single Port SRAM Memory Compiler using 213 bit-cell with Peri-LVT
UMC 40nm LP Logic Process Single Port SRAM Memory Compiler using 213 bit-cell with Peri-LVT
UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT
UMC 40nm LP Logic Process Single Port SRAM memory compiler using 213 bit -cell with peri-HVT
UMC 40nm Low Power Process SP-SRAM with 213 bit cell
UMC 40nm Low Power Process SP-SRAM with 213 bit cell
UMC 28nm HPC Process Ultra High Speed Single-Port SRAM Memory Compiler
UMC 28nm HPC Process Ultra High Speed Single-Port SRAM Memory Compiler
UMC 28nm HPC Process Ultra High Speed Single-Port SRAM memory compiler
UMC 28nm HPC Process Ultra High Speed Single-Port SRAM memory compiler
28nm HPM SH with Row redundancy
28nm HPM SH with Row redundancy
28nm HPM SP-SRAM with peri LVT row repair
28nm HPM SP-SRAM with peri LVT row repair
28nm HPM SP-SRAM with peri LVT
28nm HPM SP-SRAM with peri LVT
UMC 28nm HPM process standard synchronous high density single port SRAM memory compiler
UMC 28nm HPM process standard synchronous high density single port SRAM memory compiler
UMC 28nm HPC process standard synchronous high density single port low power SRAM memory compiler with row redundancy
UMC 28nm HPC Logic Process PG Single Port SRAM with LVT memory compiler
UMC 28nm HPC Logic Process PG Single Port SRAM with LVT memory compiler
UMC 28nm HPC Logic Process PG Single-Port SRAM with HVT memory compiler
UMC 28nm HPC Logic Process PG Single-Port SRAM with HVT memory compiler