How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
SmartDV Technologies
Category:
DDR
DDR5 Synthesizable Transactor
DDR5 Synthesizable Transactor provides a smart way to verify the DDR5 component of a SOC or a ASIC in Emulator or FPGA platform.
Overview
DDR5 Synthesizable Transactor provides a smart way to verify the DDR5 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's DDR5 Synthesizable Transactor is fully compliant with standard DDR5 Specification and provides the following features.
Key features
- Supports 100% of DDR5 protocol standard JESD79-5 & JESD79-5 Rev1.40 (Draft)
- Supports all the DDR5 commands as per the specs
- Supports up to 64GB device density
- Supports the following devices:
- X4
- X8
- X16
- Supports all speed grades as per specification
- Supports Write Pattern command
- Supports Auto precharge for Write,Read and Write pattern command.
- Supports CA, CS and Read Preamble training modes
- Supports MIR and CAI operations
- Supports Read training pattern
- Supports Write leveling training mode
- Supports Programmable Write latency and Read latency
- Supports Programmable Preamble, Postamble and Interamble
- Supports Programmable burst lengths: 8, 16, 32
- Supports Sequential burst type and Burst order
- Supports 2N mode
- Supports all mode registers programming
- Supports Write data mask
- Supports CRC for Write,Read and MRR operations
- Supports for DLL features
- Checks for following
- Check-points include power up, initialization and power off rules
- State based rules, Active Command rules
- Read/Write Command rules etc.,
- All timing violations
- Supports Self Refresh and Power down operation
- Supports Partial Array Self Refresh (PASR)
- Supports Refresh modes and Global refresh counter
- Supports Refresh management all command
- Supports Adaptive Refresh Management (ARFM).
- Supports Directed Refresh Management (DRFM).
- Supports Refresh management same bank command
- Supports for temperature compensated refresh reporting
- Supports Maximum power saving mode
- Supports Post Package Repair (PPR).
- Supports hard Post Package Repair (hPPR)
- Supports soft Post Package Repair (sPPR)
- Supports Memory Built-In Self Test-Post Package Repair (mPPR)
- Supports Loop back concepts
- Supports Target Row Refresh
- Supports Per DRAM Addressability
- Supports Precharge command modes
- Supports Multipurpose Command (MPC)
- Supports VrefCA command
- Supports VrefCS command
- Supports ZQ calibration
- Supports Vref CA, Vref CS and Vref DQ training
- Supports On-Die Termination (ODT)
- Supports Connectivity Test (CT) mode
- Supports all types of timing and protocol violation detection
- Models, detects and notifies the test bench of significant events such as transactions warnings, timing and protocol violations
Block Diagram
DDR5 Transactor block diagram
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
What’s Included?
- Synthesizable transactors
- Complete regression suite containing all the DDR5 testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes
Specifications
Identity
Part Number
DDR5 Transactor
Vendor
SmartDV Technologies
Type
Silicon IP
Controller / PHY
Controller
Standards & Interfaces
Memory
DDR5
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
India
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Frequently asked questions about DDR Interface IP
What is DDR5 Synthesizable Transactor?
DDR5 Synthesizable Transactor is a DDR IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.