How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
SmartDV Technologies
Category:
DDR
DDR5 DFI Assertion IP
DDR5 DFI Assertion IP provides an efficient and smart way to verify the DDR5 DFI designs quickly without a testbench.
Overview
DDR5 DFI Assertion IP provides an efficient and smart way to verify the DDR5 DFI designs quickly without a testbench. The SmartDV's DDR5 DFI Assertion IP is fully compliant with standard DFI 5.0 Specification.
DDR5 DFI Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
DDR5 DFI Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Key features
- Specification Compliance
- Compliant with DFI 5.0 Specification.
- DFI DDR5 Applies to :
- DDR5 protocol standard JESD79-5 & JESD79-5 Rev1.40 (Draft) Specifications
- Supports all Interface Groups.
- Supports Write Transactions with Data mask/Write DBI.
- Supports Write Transactions with data CRC
- Supports Read Transactions with CRC.
- Supports Data bit enable/disable feature.
- Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio.
- Supports Low power control features.
- Supports Error signaling.
- Supports DFI Read/Write Chip Select.
- Supports 3DS Stack.
- Supports Inactive CS.
- Supports all types of timing and protocol violations detection for timing parameters like tphy_wrlat ,tphy_wrdata,trd_dataen and tphy_rdlat delays
- Constantly monitors DFI behavior during simulation.
- Assertion IP features
- Assertion IP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Control mode, Phy mode, Monitor mode and Constraint mode
- Supports Simulation mode (stimulus from SmartDV DDR5 DFI Interface) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure DDR5 DFI AIP functionality
Block Diagram
DDR5 DFI AIP block diagram
Benefits
- Runs in every major formal and simulation environment.
What’s Included?
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
Specifications
Identity
Part Number
DDR5 DFI AIP
Vendor
SmartDV Technologies
Type
Silicon IP
Controller / PHY
Controller
Standards & Interfaces
Memory
DDR5
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
India
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Frequently asked questions about DDR Interface IP
What is DDR5 DFI Assertion IP?
DDR5 DFI Assertion IP is a DDR IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.