How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
SmartDV Technologies
Category:
DDR
DDR5 Assertion IP
DDR5 Assertion IP provides an efficient and smart way to verify the DDR5 designs quickly without a testbench.
Overview
DDR5 Assertion IP provides an efficient and smart way to verify the DDR5 designs quickly without a testbench. The SmartDV's DDR5 Assertion IP is fully compliant with standard DDR5 Specification.
DDR5 Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
DDR5 Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Key features
- Specification Compliance
- Supports DDR5 memory devices from all leading vendors.
- Supports 100% of DDR5 protocol standard JESD79-5 & JESD79-5 Rev1.40 (Draft).
- Supports all the DDR5 commands as per the specs.
- Supports up to 64GB device density.
- Supports the following devices.
- X4
- X8
- X16
- Supports all speed grades as per specification.
- Supports Write Pattern command.
- Supports Auto precharge for Write, Read and Write pattern command.
- Supports CA, CS and Read Preamble training modes.
- Supports MIR and CAI operations.
- Supports Read training pattern.
- Supports Write leveling training mode.
- Supports Programmable Write latency and Read latency.
- Supports Programmable Preamble, Postamble and Interamble.
- Supports Programmable burst lengths: 8, 16, 32.
- Supports Sequential burst type and Burst order.
- Supports 2N mode.
- Supports all mode register programming.
- Supports Write data mask.
- Supports CRC for Write, Read and MRR operations.
- Supports DLL features.
- Checks for following
- Check-points include power up, Initialization and power off rules
- State based rules, Active Command rules
- Read/Write Command rules etc.,
- All timing violations
- Supports Self Refresh and Power down operation.
- Supports Partial Array Self Refresh (PASR).
- Supports Self Refresh Entry with frequency change (SREF)
- Supports Refresh modes and Global refresh counter.
- Supports Refresh management all command.
- Supports Adaptive Refresh Management (ARFM).
- Supports Directed Refresh Management (DRFM).
- Supports Refresh management same bank command.
- Supports for temperature compensated refresh reporting
- Supports Maximum power saving mode.
- Supports Post Package Repair (PPR).
- Supports hard Post Package Repair (hPPR)
- Supports soft Post Package Repair (sPPR)
- Supports Memory Built-In Self Test-Post Package Repair (mPPR)
- Supports Loop back concepts.
- Supports Target row refresh
- Supports per DRAM Addressability.
- Supports Precharge command modes.
- Supports Multipurpose Command (MPC).
- Supports VrefCA command.
- Supports VrefCS command.
- Supports Vref CA, Vref CS and Vref DQ training.
- Supports ZQ calibration
- Supports input clock stop and frequency change.
- Supports On-Die Termination (ODT).
- Supports Connectivity Test (CT) mode.
- Supports all timing delay ranges in one model: min, typical and max.
- Protocol checker fully compliant with DDR5 Specifications JESD79-5 & JESD79-5 Rev1.40 (Draft).
- Constantly monitors DDR5 behavior during simulation.
- Assertion IP features
- AIP includes:
- System Verilog assertions.
- System Verilog assumptions.
- System Verilog cover properties.
- Synthesizable Verilog Auxiliary code.
- Supports Control mode, Model mode, Monitor mode and Constraint mode.
- Supports Simulation mode (stimulus from SmartDV DDR5 VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure DDR5 AIP functionality.
Block Diagram
DDR5 AIP block diagram
Benefits
- Runs in every major formal and simulation environment.
What’s Included?
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
Specifications
Identity
Part Number
DDR5 AIP
Vendor
SmartDV Technologies
Type
Silicon IP
Controller / PHY
Controller
Standards & Interfaces
Memory
DDR5
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
India
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Frequently asked questions about DDR Interface IP
What is DDR5 Assertion IP?
DDR5 Assertion IP is a DDR IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.