How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
SmartDV Technologies
Category:
DDR
DDR4 Synthesizable Transactor
DDR4 Synthesizable Transactor provides a smart way to verify the DDR4 component of a SOC or a ASIC in Emulator or FPGA platform.
Overview
DDR4 Synthesizable Transactor provides a smart way to verify the DDR4 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's DDR4 Synthesizable Transactor is fully compliant with standard DDR4 Specification and provides the following features.
Key features
- Supports 100% of DDR4 protocol standard JESD79-4, JESD79-4A, JESD79-4A_r2, JESD79-4B, JESD79-4C and JESD79-4D(Draft)
- Supports all the DDR4 commands as per the specs
- Supports up to 16GB device density
- Supports X4,X8,X16 and X32 devices
- Supports all speed grades as per specification
- Supports On-the-fly protocol and data checking
- Supports Programmable Write latency and Read latency
- Supports Programmable burst lengths: 4,8
- Supports Programmable Preamble
- Supports Read preamble training
- Supports the following burst types:
- Sequential
- Interleave
- Supports burst order
- Checks for following:
- Check-points include power up, initialization and power off rules
- State based rules, Active Command rules
- Read/Write Command rules etc.,
- All timing violations
- Supports all mode register programming
- Supports Data Mask and Data Bus Inversion (DBI)
- Supports write leveling for calibrations and ZQ Calibration commands
- Supports Fine Granularity Refresh Mode
- Supports Multipurpose Register
- Supports DQ Vref training
- Supports CRC for Write Operations
- Supports DLL features
- Supports Command Address Parity features
- Supports Post Package Repair (PPR)
- Supports Control Gear down mode and CAL Mode Operation
- Supports Per DRAM Addressability
- Supports Connectivity Test (CT) mode
- Supports MBIST PPR.
- Supports Power Down features and Maximum Power Saving mode
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
Block Diagram
DDR4 Transactor block diagram
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
What’s Included?
- Synthesizable transactors
- Complete regression suite containing all the DDR4 testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes
Specifications
Identity
Part Number
DDR4 Transactor
Vendor
SmartDV Technologies
Type
Silicon IP
Controller / PHY
Controller
Standards & Interfaces
Memory
DDR4
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
India
Learn more about DDR IP core
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Frequently asked questions about DDR Interface IP
What is DDR4 Synthesizable Transactor?
DDR4 Synthesizable Transactor is a DDR IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.