How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
SmartDV Technologies
Category:
DDR
DDR4 DFI Verification IP
DDR4 DFI Verification IP provides an smart way to verify the DDR4 DFI component of a SOC or a ASIC.
Overview
DDR4 DFI Verification IP provides an smart way to verify the DDR4 DFI component of a SOC or a ASIC. The SmartDV's DDR4 DFI Verification IP is fully compliant with standard DFI Specification and provides the following features.
DDR4 DFI Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
DDR4 DFI Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Key features
- Compliant with DFI version 3.0 or higher Specifications.
- DFI-DDR4 Applies to :
- DDR4 protocol standard JESD79-4, JESD79-4A, JESD79-4A_r2,JESD79-4B, JESD79-4C and JESD79-4D (draft) Specification
- Supports all Interface Groups.
- Supports for PHY master(DFI bus control by PHY)
- Supports Write Transactions with DBI, DM.
- Supports Read Transactions with DBI.
- Supports DRAM Clock disabling feature.
- Supports Data bit enable/disable feature.
- Supports Cyclic Redundancy check with Write data transmission.
- Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio.
- Supports frequency change protocol.
- Supports CA Parity Signaling.
- Supports Low power control features.
- Supports Error signaling.
- Supports Training interface
- Gate Training
- Read data eye training
- Write leveling
- Write DQ Training
- Supports Gear down Mode (2T Mode).
- Supports 3DS Stack.
- Supports Inactive CS.
- Supports all types of timing and protocol violations detection for timing parameters like tphy_wrlat ,tphy_wrdata,trd_dataen and tphy_rdlat delays Constantly monitors DFI behavior during simulation.
- Protocol checker fully compliant with DFI version 3.0 or higher Specifications.
- Bus-accurate timing for min, max and typical values.
- Notifies the test bench of significant events such as transactions, warnings
- Built in functional coverage analysis.
- Supports callbacks, so that user can access the data observed by monitor.
Block Diagram
DDR4 DFI VIP block diagram
Benefits
- Faster test bench development and more complete verification of DDR4 DFI designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
What’s Included?
- Complete regression suite containing all the DDR4 DFI testcases.
- Complete UVM/OVM sequence library for DDR4 DFI controller.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all classes, tasks and functions used in verification env.
- Documentation also contains User's Guide and Release notes.
Specifications
Identity
Part Number
DDR4 DFI VIP
Vendor
SmartDV Technologies
Type
Verification IP
Controller / PHY
Controller
Standards & Interfaces
Memory
DDR4
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
India
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Frequently asked questions about DDR Interface IP
What is DDR4 DFI Verification IP?
DDR4 DFI Verification IP is a DDR IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.