How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
SmartDV Technologies
Category:
DDR
DDR4 DFI Synthesizable Transactor
DDR4 DFI Synthesizable Transactor provides a smart way to verify the DDR4 DFI component of a SOC or a ASIC in Emulator or FPGA pl…
Overview
DDR4 DFI Synthesizable Transactor provides a smart way to verify the DDR4 DFI component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's DDR4 DFI Synthesizable Transactor is fully compliant with standard DDR4 DFI version 3.0 or higher Specifications and provides the following features.
Key features
- Compliant with DFI version 3.0 or higher Specifications.
- DFI-DDR4 Applies to :
- DDR4 protocol standard JESD79-4, JESD79-4A, JESD79-4A_r2,JESD79-4B, JESD79-4C and JESD79-4D (draft) Specification
- Supports all Interface Groups.
- Supports for PHY master(DFI bus control by PHY)
- Supports Write Transactions with DBI, DM.
- Supports Read Transactions with DBI.
- Supports DRAM Clock disabling feature.
- Supports Data bit enable/disable feature.
- Supports Cyclic Redundancy check with Write data transmission.
- Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio.
- Supports frequency change protocol.
- Supports CA Parity Signaling.
- Supports Low power control features.
- Supports Error signaling.
- Supports Training interface
- Gate Training
- Read data eye training
- Write leveling
- Write DQ Training
- Supports Gear down Mode (2T Mode).
- Supports 3DS Stack.
- Supports Inactive CS.
- Supports all types of timing and protocol violation detection
- Checks for following
- Power on, Initialization and Power off rules
- State based rules, Active Command rules
- Read/Write Command rules
- All timing violations
Block Diagram
DDR4 DFI Transactor block diagram
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
What’s Included?
- Synthesizable transactors
- Complete regression suite containing all the DDR4 DFI testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes
Specifications
Identity
Part Number
DDR4 DFI Transactor
Vendor
SmartDV Technologies
Type
Silicon IP
Controller / PHY
Controller
Standards & Interfaces
Memory
DDR4
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
India
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Frequently asked questions about DDR Interface IP
What is DDR4 DFI Synthesizable Transactor?
DDR4 DFI Synthesizable Transactor is a DDR IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.