DDR4 DFI Assertion IP

DDR4 DFI Assertion IP provides an efficient and smart way to verify the DFI DDR4 designs quickly without a testbench. The SmartDV's DDR4 DFI Assertion IP is fully compliant with DFI version 3.0 or higher Specifications.

DDR4 DFI Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

DDR4 DFI Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

• Specification Compliance
• Compliant with DFI version 3.0 or higher Specifications.
• DFI-DDR3 Applies to :
• DDR3 protocol standard JESD79-3F Specification
• Supports all the Interface Groups.
• Supports Write Transactions with DM
• Supports Data bit enable/disable feature.
• Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio.
• Supports DFI Read/Write Chip Select.
• Supports Training interface
• Gate Training
• Read data eye training
• Write leveling
• Write DQ Training
• Supports Low power control features.
• Supports Error signaling.
• Supports Per-Slice Read Leveling.
• Supports Inactive CS.
• Supports all types of timing and protocol violations detection for timing parameters like tphy_wrlat ,tphy_wrdata,trd_dataen and tphy_rdlat delays
• Constantly monitors DFI behavior during simulation.
• Protocol checker fully compliant with DFI version 3.0 or higher Specifications
• Assertion IP features
• Assertion IP includes:
• System Verilog assertions
• System Verilog assumptions
• System Verilog cover properties
• Synthesizable Verilog Auxiliary code
• Support Control mode, PHY mode, Monitor mode and Constraint mode.
• Supports Simulation mode (stimulus from SmartDV DFI DDR4 VIP) and Formal mode (stimulus from Formal tool).
• Rich set of parameters to configure DFI DDR4 Assertion IP functionality.

• Runs in every major formal and simulation environment.

• Detailed documentation of Assertion IP usage.
• Documentation also contains User's Guide and Release notes.