How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Synopsys, Inc.
Category:
DDR
DDR4/3 PHY - SS 10LPP
The DDR4/3 PHY is a physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applicat…
Overview
The DDR4/3 PHY is a complete physical layer IP interface (PHY) solution for enterprise-class ASIC, ASSP, and system-on-chip (SoC) applications requiring high-performance DDR4/DDR3/DDR3L SDRAM interfaces operating at up to 3200 Mbps. The DDR4/3 PHY is ideal for systems that require high-speed DDR3/4 performance requiring high capacity memory solutions, typically using registered and load reduced memory modules (RDIMMs and LRDIMMs) with up to 16 ranks. Direct SDRAM on PCB systems are also supported.
Optimized for high performance, low latency, low area, low power, and ease of integration, the DDR4/3 PHY is provided as a hard DDR PHY that is primarily delivered as GDSII including integrated application-specific DDR4/3 I/Os. Supporting the GDSII-based PHY is the RTL-based PHY Utility Block (PUB) that includes PHY control features such as read/write leveling, data eye training, per-bit data deskew control, PVT compensation, and support for production testing of the DDR4/3 PHY. The PUB also includes an embedded calibration processor to execute hardware-assisted, firmware-based training algorithms. The DDR4/3 PHY includes a DFI 4.0 interface to the memory controller and can be combined with the Enhanced Universal Memory (uMCTL2) or Protocol (uPCTL2) controllers for a complete DDR interface solution.
Key features
- Supports JEDEC standard DDR4, DDR3, and DDR3L SDRAMs
- High-performance DDR PHY supporting data rates up to 3200 Mbps
- Compatible with JEDEC compliant DDR3/4 UDIMMs and RDIMMs as well as DDR4 LRDIMMs
- Supports up to 16 logical ranks for high capacity memory requirements
- PHY independent, firmware-based training using an embedded calibration processor
- Supports up to 4 trained states/frequencies with <5us switching time
- I/O receiver decision feedback equalization and driver feed-forward equalization
- VT compensated delay lines for DQS centering, read/write leveling, and per bit deskew
- DFI 4.0-compliant controller interface
- Designed for rapid integration with Synopsys memory or protocol controllers for a complete DDR interface solution
Block Diagram
dwc_ddr4_ddr3_phy_ss10lpp block diagram
Specifications
Identity
Part Number
dwc_ddr4_ddr3_phy_ss10lpp
Vendor
Synopsys, Inc.
Type
Silicon IP
Controller / PHY
Controller + PHY
,
PHY
Standards & Interfaces
Memory
DDR4
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about DDR Interface IP
What is DDR4/3 PHY - SS 10LPP?
DDR4/3 PHY - SS 10LPP is a DDR IP core from Synopsys, Inc. listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.