How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
SmartDV Technologies
Category:
DDR
DDR3 Synthesizable Transactor
DDR3 Synthesizable Transactor provides a smart way to verify the DDR3 component of a SOC or a ASIC in Emulator or FPGA platform.
Overview
DDR3 Synthesizable Transactor provides a smart way to verify the DDR3 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's DDR3 Synthesizable Transactor is fully compliant with standard DDR3 Specification and provides the following features.
Key features
- Supports 100% of DDR3 protocol standard JESD79-3F
- Supports all the DDR3 commands as per the specs
- Supports up to 8 GB device density:
- Supports following devices:
- X4
- X8
- X16
- Supports all speed grades as per specification
- Supports programmable write latency and read latency
- Supports 8 internal banks
- Supports programmable burst lengths: 4, 8
- Supports following burst order:
- Sequential
- Interleave
- Checks for following:
- Check-points include power up,initialization and power off rules
- State based rules, active command rules
- Read/Write command rules etc
- All timing violations
- Supports all mode registers programming
- Supports write data mask
- Supports power down features
- Supports automatic self refresh
- Supports self refresh modes
- Supports DLL
- Supports write leveling
- Supports ZQ calibration
- Supports ODT(On-Die Termination)
- Supports full-timing as well as behavioral versions in one model
- Supports all timing delay ranges in one model: min, typical and max
- Supports on-the-fly for burst length
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
Block Diagram
DDR3 Transactor block diagram
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
What’s Included?
- Synthesizable transactors
- Complete regression suite containing all the DDR3 testcases
- Examples's showing how to connect and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation also contains User's Guide and Release notes
Specifications
Identity
Part Number
DDR3 Transactor
Vendor
SmartDV Technologies
Type
Silicon IP
Controller / PHY
Controller
Standards & Interfaces
Memory
DDR3
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
India
Learn more about DDR IP core
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Frequently asked questions about DDR Interface IP
What is DDR3 Synthesizable Transactor?
DDR3 Synthesizable Transactor is a DDR IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.