DDR3 DFI Synthesizable Transactor

DDR3 DFI Synthesizable Transactor provides a smart way to verify the DDR3 DFI component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's DDR3 DFI Synthesizable Transactor is fully compliant with standard DDR3 DFI version 2.0 or higher Specifications and provides the following features.

• Compliant with DFI version 2.0 or higher Specifications.
• DFI-DDR3 Applies to :
• DDR3 protocol standard JESD79-3F Specification
• Supports all the Interface Groups.
• Supports Write Transactions with DM
• Supports DRAM Clock disabling feature.
• Supports Data bit enable/disable feature.
• Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio.
• Supports frequency change protocol.
• Supports DFI Read/Write Chip Select.
• Supports Training interface
• Gate Training
• Read data eye training
• Write leveling
• Write DQ Training
• Supports Low power control features.
• Supports Error signaling.
• Supports Per-Slice Read Leveling.
• Supports Inactive CS.
• Supports all types of timing and protocol violation detection
• Checks for following
• Power on, Initialization and Power off rules
• State based rules, Active Command rules
• Read/Write Command rules
• All timing violations

• Compatible with testbench writing using SmartDV's VIP
• All UVM sequences/testcases written with VIP can be reused
• Runs in every major emulators environment
• Runs in custom FPGA platforms

• Synthesizable transactors
• Complete regression suite containing all the DDR3 DFI testcases
• Examples showing how to connect various components, and usage of Synthesizable Transactor
• Detailed documentation of all DPI, class, task and function's used in verification env
• Documentation contains User's Guide and Release notes