How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
SmartDV Technologies
Category:
DDR
DDR3 Assertion IP
DDR3 Assertion IP provides an efficient and smart way to verify the DDR3 designs quickly without a testbench.
Overview
DDR3 Assertion IP provides an efficient and smart way to verify the DDR3 designs quickly without a testbench. The SmartDV's DDR3 Assertion IP is fully compliant with standard DDR3 Specification.
DDR3 Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
DDR3 Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
Key features
- Specification Compliance
- Compliant to DDR3 protocol specification
- Different DDR3 burst lengths of 4 or 8
- All signal level checks including x detection
- Supports all DDR3 legal address and bank address widths
- Supports CAS latency
- Supports all legal values of auto precharge for each burst
- Supports different additive latency values
- Supports mode register set command
- Support for check-points include power on, Initialization and power off rules,
- Support for state based rules, Active Command rules,
- Support for Read/Write Command rules etc.
- Support for all timing violations.
- Assertion IP features
- Assertion IP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Master mode, Slave mode, Monitor mode and Constraint mode.
- Supports Simulation mode (stimulus from SmartDV DDR3 VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure DDR3 Assertion IP functionality.
Block Diagram
DDR3 AIP block diagram
Benefits
- Runs in every major formal and simulation environment.
What’s Included?
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
Specifications
Identity
Part Number
DDR3 AIP
Vendor
SmartDV Technologies
Type
Silicon IP
Controller / PHY
Controller
Standards & Interfaces
Memory
DDR3
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
India
Learn more about DDR IP core
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Frequently asked questions about DDR Interface IP
What is DDR3 Assertion IP?
DDR3 Assertion IP is a DDR IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.