How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
SmartDV Technologies
Category:
DDR
DDR2 Synthesizable Transactor
DDR2 Synthesizable Transactor provides a smart way to verify the DDR2 component of a SOC or a ASIC in Emulator or FPGA platform.
Overview
DDR2 Synthesizable Transactor provides a smart way to verify the DDR2 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's DDR2 Synthesizable Transactor is fully compliant with standard JESD79-2F Specification and provides the following features.
Key features
- Supports 100% of DDR2 protocol standard JESD79-2F
- Supports all the DDR2 commands as per the specs
- Supports double data rate interface
- Supports up to 4 GB device density
- Supports 8 internal banks
- Supports following devices:
- X4
- X8
- X16
- Supports all speed grades as per specification
- Supports programmable Write latency and read latency
- Supports programmable burst lengths: 4,8
- Supports following burst types:
- Sequential
- Interleave
- Supports burst sequence
- Checks for following:
- Check-points include power up,initialization and power off rules
- State based rules, active Command rules
- Read/Write command rules etc
- All timing violations
- Supports all mode registers programming
- Supports extended mode registers programming
- Supports write data mask
- Supports power down features
- Supports self refresh mode
- Supports auto precharge option for each burst access
- Supports ODT(On-Die Termination)
- Supports DLL
- Supports full-timing as well as behavioral versions in one model
- Supports all timing delay ranges in one model: min, typical and max
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
Block Diagram
DDR2 Transactor block diagram
Benefits
- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
What’s Included?
- Synthesizable transactors
- Complete regression suite containing all the DDR2 testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes
Specifications
Identity
Part Number
DDR2 Transactor
Vendor
SmartDV Technologies
Type
Silicon IP
Controller / PHY
Controller
Standards & Interfaces
Memory
DDR2
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
India
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Frequently asked questions about DDR Interface IP
What is DDR2 Synthesizable Transactor?
DDR2 Synthesizable Transactor is a DDR IP core from SmartDV Technologies listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.