The Platform Based SOC Design that Utilizes Structured ASIC Technology
The Platform Based SOC Design that Utilizes Structured ASIC Technology
Vendor:
Faraday Technology
Category:
DLL
DDR DLL (All Digital) IP, Input: 800MHz - 1600MHz, Output: 800MHz - 1600MHz, UMC 28nm HPM process
Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 2…
Overview
Input 800M-1600MHz, output 800M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF, UMC 28nm Logic and Mixed-Mode HPM process.
Silicon Options
| Foundry | Node | Process | Maturity |
|---|---|---|---|
| UMC | 28nm | HPM | — |
Specifications
Identity
Part Number
FXADDLL340HJ0G
Vendor
Faraday Technology
Type
Silicon IP
Provider
HQ:
Taiwan
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Frequently asked questions about DLL IP cores
What is DDR DLL (All Digital) IP, Input: 800MHz - 1600MHz, Output: 800MHz - 1600MHz, UMC 28nm HPM process?
DDR DLL (All Digital) IP, Input: 800MHz - 1600MHz, Output: 800MHz - 1600MHz, UMC 28nm HPM process is a DLL IP core from Faraday Technology listed on Semi IP Hub. It is listed with support for umc.
How should engineers evaluate this DLL?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DLL IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.