Testmux 5bit - TSMC 180nm
- TSMC
- 180nm
- BCDG2
- Silicon Proven
Control Logic Accelerator IP cores accelerate state-machine-heavy and control-oriented processing tasks in modern SoC and ASIC designs.
These IP cores help offload control-path work, scheduling, sequencing, and real-time coordination from general-purpose processors in complex datapaths
This catalog allows you to compare Control Logic Accelerator IP cores from leading vendors based on latency, determinism, integration flexibility, and process node compatibility.
Whether you are designing embedded control systems, communications pipelines, industrial automation, or accelerator orchestration, you can find the right Control Logic Accelerator IP for your application.
Testmux 5bit - TSMC 180nm
Testmux 4bit - GlobalFoundries 130nm RFSOI
Testmux 4bit - GlobalFoundries 130nm RFSOI
Binary to Thermocoder, 5bit - GlobalFoundries 130nm RFSOI
Binary to Thermocoder, 5bit - GlobalFoundries 130nm RFSOI
Binary to Thermocoder, 4bit - GlobalFoundries 130nm RFSOI
Binary to Thermocoder, 4bit - GlobalFoundries 130nm RFSOI
Binary to Thermocoder, 3bit - GlobalFoundries 130nm RFSOI
Binary to Thermocoder, 3bit - GlobalFoundries 130nm RFSOI
Binary to One-hot coder, 4bit - GlobalFoundries 130nm RFSOI
Binary to One-hot coder, 4bit - GlobalFoundries 130nm RFSOI
Binary to One-hot coder, 3bit - GlobalFoundries 130nm RFSOI
Binary to One-hot coder, 3bit - GlobalFoundries 130nm RFSOI
Binary to One-hot coder, 2bit - GlobalFoundries 130nm RFSOI
Binary to One-hot coder, 2bit - GlobalFoundries 130nm RFSOI
RF Counter, 8b - GlobalFoundries 40nm
RF Counter, 8b - GlobalFoundries 40nm
RF Counter, 16b - GlobalFoundries 55nm
RF Counter, 16b - GlobalFoundries 55nm
Xilinx provided utility function to simplify design in Vivado IP Integrator.
Xilinx provided utility function to simplify design in Vivado IP Integrator.
Xilinx provided utility function to simplify design in Vivado IP Integrator.
Xilinx provided utility function to simplify design in Vivado IP Integrator.
Xilinx provided utility function to simplify design in Vivado IP Integrator.
The Reduced Logic module is designed to be used with Platform Studio to perform simple logical operations.
The flip-flop logic is designed to be used with Platform Studio to perform simple logical operations.
The Bus Split operation is designed to be used with Platform Studio to split a bus into smaller buses.
Register, Configuration and Control Bus
A2R provides an interconnection mechanism between control registers in an ASIC design and any number of control devices; CPUs, de…
Digital PID Controller Loop Algorithms for EMA
We have developed control system algorithm IP blocks to be able to control electromagnetic actuators.