Vendor: SmartDV Category: Protocol Bridge

Avalon Assertion IP

Avalon Assertion IP provides an smart way to verify the Avalon Interface.

Overview

Avalon Assertion IP provides an smart way to verify the Avalon Interface. The SmartDV Assertion IP for Avalon interface is fully compliant with Intel's Avalon Interface specification.Avalon Interface Specification and provides the following features

Avalon Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

Avalon Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key features

  • Specification Compliance
    • Compliant with Intel's Avalon Interface specification.
    • Supported interfaces and components:
    • Avalon Memory-Mapped (Avalon-MM) Master and Slave interfaces
    • Avalon Streaming (Avalon-ST) Source and Sink interfaces
    • Avalon Conduit interfaces
    • Avalon Tristate Conduit (Avalon-TC) interfaces
    • Avalon Interrupt Source and Sink interfaces
    • Avalon Clock Source and Sink interfaces
    • Avalon Reset Source and Sink interfaces
    • Avalon-MM Interface support
    • Supports all address and data widths
    • Supports all Typical, Pipelined and Burst transfer types
    • Avalon-ST Interface support
    • Supports all transfer types.
    • Avalon Conduit Interface support
    • Supports to connect individual or group of non-avalon signals.
    • Avalon-TC Interface support
    • Supports to reduce the number of signals and pin count.
    • Avalon Interrupt Interface support
    • Supports point to point connection between two systems
  • Assertion IP features
    • Assertion IP includes:
    • System Verilog assertions
    • System Verilog assumptions
    • System Verilog cover properties
    • Synthesizable Verilog Auxiliary code
    • Support Master mode, Slave mode, Monitor mode and Constraint mode.
    • Supports Simulation mode (stimulus from SmartDV Avalon VIP) and Formal mode (stimulus from Formal tool).
    • Rich set of parameters to configure Avalon Assertion IP functionality.

Block Diagram

Avalon AIP block diagram

Benefits

  • Runs in every major formal and simulation environment.

What’s Included?

  • Detailed documentation of Assertion IP usage.
  • Documentation also contains User's Guide and Release notes.

Specifications

Identity

Part Number
Avalon AIP
Vendor
SmartDV
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

SmartDV
HQ: India

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Frequently asked questions about Protocol Bridge IP cores

What is Avalon Assertion IP?

Avalon Assertion IP is a Protocol Bridge IP core from SmartDV listed on Semi IP Hub.

How should engineers evaluate this Protocol Bridge?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Protocol Bridge IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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