DCDC regu power stage, includes bootstrap regulator
DCDC regu power stage, includes bootstrap regulator
- TSMC
- 180nm
- BCDG2
- Silicon Proven
Analog and Mixed-Signal IP cores are essential building blocks in modern SoC and ASIC designs, enabling seamless interaction between analog signals and digital processing.
These IP cores are widely used for data conversion (ADC, DAC), clock generation (PLL, oscillators), power management, and sensors & monitors such PVT monitors.
This catalog allows you to compare analog and mixed-signal IP cores from leading vendors by performance, power consumption, process node compatibility, and application domain.
Whether you are designing for wireless communication, automotive systems, consumer electronics, or industrial IoT, you can find the most suitable IP solutions for your requirements.
DCDC regu power stage, includes bootstrap regulator
DCDC regu power stage, includes bootstrap regulator
LS current replica block, 1:100'000
LS current replica block, 1:100'000, for LS switch current measurement
HS current replica block, 1:100'000
HS current replica block, 1:100'000, for HS switch current measurement
Ripple injector, feedback block for regulator output ripple measurement
LS power switch driver
HS power switch driver
HS bootstrap driver for HS NMOS gate voltage generation
HS bootstrap driver for HS NMOS gate voltage generation
20ns rising edge delay circuit, RC-based, trimmable
20ns rising edge delay circuit, RC-based, trimmable
150ns rising edge delay circuit, not trimmable
150ns rising edge delay circuit, bias current to C based, not trimmable
10ns rising edge delay circuit, RC-based, trimmable
10ns rising edge delay circuit, RC-based, trimmable
Adjustable delay block for dual-phase regulator operation
Adjustable delay block for dual-phase regulator operation
Inverter based delay chain, 5ns
Inverter based delay chain, 5ns
Inverter based delay chain, 10ns
Inverter based delay chain, 10ns
Zero-cross detector and valley OCP block, trimmable
Zero-cross detector and valley OCP block, trimmable
HS current protection circuit
Current monitor circuit, Vout=1.2V+0.06V*Iload
Current monitor circuit, Vout=1.2V+0.06V*Iload
10-bit 1MHz R-2R DAC, VREF=2.56V, voltage step = 2.5mV, INL
Charge pump, makes Vin-3.3V voltage
Charge pump, makes Vin-3.3V voltage
Voltage sense comparator, relatively slow, <10mV offset
Voltage sense comparator, relatively slow,
Error comparator, for PWM generation in the DCDC
Error comparator, forms base for PWM generation in the DCDC regu