Power on Reset with ultra low standby current
- Power On Reset (POR)
Power management IP cores are essential components in modern SoC and ASIC designs, enabling efficient power regulation, distribution, and energy optimization.
These IP cores include functions such as voltage regulators, DC-DC converters, LDOs, battery management, and power monitoring, ensuring reliable and energy-efficient system operation.
This catalog allows you to compare power management IP cores from leading vendors based on efficiency, power consumption, integration level, and process node compatibility.
Whether you are designing mobile devices, automotive systems, IoT products, or high-performance computing platforms, you can find the right power management IP for your system.
Power on Reset with ultra low standby current
Linear regulator with ultra low standby current to provide low cost and high performance voltage regulation for low power standby…
Ultra low quiescent current SIMO (single inductor multiple output) DCDC converter to provide high efficiency voltage regulation a…
5V to 3.3V/1.8V with 80mA/40mA driving capability, Linear Regulator; UMC 0.162um GII process.
5V with 250mA driving capability, Istb=120uA Linear Regulator; 0.35um Logic process
5V with 250mA driving capability, Istb=120uA Linear Regulator; 0.35um Logic process
Vrr=1.96V Vfr=1.76V, input 3.3V, Core Type; Power On Reset; UMC 0.35um Logic process
Vrr=1.96V Vfr=1.76V, input 3.3V, Core Type; Power On Reset; UMC 0.35um Logic process
Power Management Unit(5-sets DC-DC, 2-sets REG, PowerSwitch, and Li-ion Charger) for Audio Platform; UMC 0.35um 3.3V/5V CDMOS pro…
8V ~ 25V HV driver, UMC 0.35um 3.3V/5V/40V CDMOS logic process
8V ~ 25V HV driver, UMC 0.35um 3.3V/5V/40V CDMOS logic process
5V to 4.2V battery charger with 3.3V device ; UMC 0.153um Logic/Mixed-Mode Process
5V to 4.2V battery charger with 3.3V device ; UMC 0.153um Logic/Mixed-Mode Process
Input 3V-3.6V, VBG=1.23V BandGap; UMC 0.35um CDMOS Process
Input 3V-3.6V, VBG=1.23V BandGap; UMC 0.35um CDMOS Process
Static current is low to 700nA; Typical POR delay time is about 1.9ms;0.0143mm2
3.3V-->1.5V capacitor-free LDO
IP
3.3V-->1.5V ultra-low power LDO
IP
Power on Reset IP, Input: 3.3V, UMC 0.5um process
Vrr=2.3V without Vfr, VCC=3.3V, Ivcc=17uA, L type IO, Power On Reset, UMC 0.5um Logic process low voltage.
Power on Reset IP, Input: 3.3V, UMC 0.5um process
Vrr=2.3V without Vfr, VCC=3.3V, Ivcc=17uA, B type IO, Power On Reset, UMC 0.5um Logic process.
Power on Reset IP, Input: 5V, UMC 0.5um process
Vrr=3.4V Vfr=3.0V, VCC=5V, Ivcc=17uA, B type IO, Power On Reset, UMC 0.5um Logic process.
Linear Regulator IP, Output: 5V/70mA, UMC 0.35um Logic process
5V with 70mA driving capability, Istb=120uA Linear Regulator, 0.35um Logic process.
DC-DC IP, Input: 3.3V, Output: +/- 12.5V / +6V, UMC 0.35um Logic process
Three pulse width modulation, boosting voltage from 3.3V to +/-12.5V, and +6V, Ivcca=450uA @ Idrive=0.
Linear Regulator IP, Output: 5V/150mA, UMC 0.35um process
5V with 150mA driving capability, Istb=120uA Linear Regulator, 0.35um Logic process.
Power on Reset IP, Input: 3.3V, UMC 0.35um process
Vrr=2.5V Vfr=2.3V, VCC=3.3V, Ivcc=18uA, Power On Reset, UMC 0.35um Logic process.